ADS1115IDGSR: 16-Bit I2C ADC Price, Stock and Datasheet Specs

The ADS1115IDGSR is Texas Instruments’ 16-bit, four-channel, I2C-addressable delta-sigma ADC in a 10-pin VSSOP (DGS) package, with a built-in programmable gain amplifier (PGA), an internal voltage reference, an oscillator, and a comparator. It samples up to 860 SPS, runs from a 2.0 V to 5.5 V supply, and resolves down to ~7.8 µV per LSB on its ±0.256 V range. If you need precise, low-speed analog measurement — battery monitoring, sensor front ends, current sensing — without burning MCU pins or board space, this is the part engineers reach for. Below: live price and stock, the specs that actually matter, and the design mistakes that cost a respin.

ADS1115IDGSR Quick Specs and Key Takeaways

• 16-bit resolution, 4 single-ended or 2 differential inputs, up to 860 samples per second.
• On-chip PGA gives 6 full-scale ranges from ±6.144 V down to ±0.256 V — no external op-amp needed for small signals.
• I2C interface with 4 selectable addresses (0x48–0x4B) via one ADDR pin, so up to four devices share a bus.
• Package: 10-pin VSSOP (DGS), 3.0 mm × 3.0 mm body, 0.5 mm pitch — small, but the fine pitch drives your stencil and DFM choices.
• Wide 2.0–5.5 V supply, ~150 µA active current; a continuous-conversion mode plus single-shot mode for low-power designs.

ADS1115IDGSR Price and Stock (Live Distributor Snapshot)

Pricing on the ADS1115IDGSR is volume-driven and moves with allocation cycles, so treat the table below as a working snapshot, not a contract. Cut-tape and small reels carry a premium; full-reel (3,000-piece) orders land at the bottom of the curve. Always confirm date code and MSL handling on the live quote.

Quantity	Typical unit price (USD)	Notes
1–9	$5.50 – $7.00	Cut tape; highest per-unit cost
10–99	$4.20 – $5.20	Small-batch prototyping
100–999	$3.10 – $4.00	Pilot / low-volume production
1,000–2,999	$2.40 – $3.00	Partial reel pricing
3,000+ (full reel)	$1.90 – $2.40	Best price break; MSL-2 dry-pack reel

Lead time runs from in-stock same-day at the major catalog distributors to 12–20 weeks during allocation. Honestly, the smartest move for a production build is to lock a date code and verify the reel is sealed MSL-2 (per J-STD-033) before you commit — a resold, baked-and-reopened reel is where field reliability quietly dies.

What Is the ADS1115IDGSR and How the 16-Bit I2C ADC Works

The ADS1115IDGSR converts an analog voltage into a 16-bit signed digital code that your microcontroller reads over I2C. Internally it is a delta-sigma converter: instead of a fast successive-approximation grab, it oversamples and noise-shapes, which is why it delivers genuine 16-bit performance at modest sample rates rather than chasing megasamples.

Three blocks do the heavy lifting. An input multiplexer routes one of four pins (AIN0–AIN3) to the core, or pairs them for differential reads. A programmable gain amplifier then scales that signal into the converter’s window. Finally the delta-sigma modulator and digital filter produce the code, which sits in a register the host pulls over I2C.

The internal reference and oscillator matter more than they look. Because the reference is on-chip, your reading is ratiometric to that reference, not to a noisy supply rail — so a 50 mV ripple on VDD does not directly corrupt your measurement the way it would on a cheaper ADC tied to VDD as its reference.

ADS1115 PGA Gain Settings and Full-Scale Ranges

The PGA is the feature people under-use. Picking the tightest range that still contains your signal multiplies your effective resolution. Here are the six settings and the resulting LSB size.

PGA setting	Full-scale range (FSR)	LSB size (µV)
2/3	±6.144 V	187.5
1	±4.096 V	125.0
2	±2.048 V	62.5
4	±1.024 V	31.25
8	±0.512 V	15.625
16	±0.256 V	7.8125

Here’s the truth, one gotcha trips up newcomers: even at the ±6.144 V setting, the absolute input voltage must never exceed VDD + 0.3 V. The ±6.144 V is a coding range, not a license to feed 6 V into a 3.3 V part. On a 3.3 V rail your real ceiling is ~3.6 V at any pin.

ADS1115 I2C Address Selection and Bus Wiring

One ADDR pin sets the 7-bit I2C address by tying it to one of four references. That lets four ADS1115IDGSR devices — 16 single-ended channels total — share a single two-wire bus, which is exactly why it beats discrete ADCs on pin-starved MCUs.

ADDR pin tied to	7-bit I2C address
GND	0x48 (default)
VDD	0x49
SDA	0x4A
SCL	0x4B

Two practical notes. First, the ADDR-to-SDA option works because the device latches the pin state at the start of each transaction — but route it cleanly, because a floating ADDR pin gives you an intermittent, maddening address. Second, size your pull-ups for the bus: 4.7 kΩ is fine at 100 kHz standard mode, but at 400 kHz fast mode with several devices and real trace capacitance you may need 2.2 kΩ to hit the rise-time spec.

ADS1115 vs ADS1015: When 16 Bits Is Worth It

The most common cross-shop is the ADS1115 against its 12-bit sibling, the ADS1015. They are pin-compatible and register-compatible, so the decision is purely resolution against speed.

Parameter	ADS1115IDGSR	ADS1015
Resolution	16-bit	12-bit
Max sample rate	860 SPS	3,300 SPS
Smallest LSB (±0.256 V)	7.8 µV	125 µV
Inputs	4 SE / 2 diff	4 SE / 2 diff
Package	VSSOP-10 (DGS)	VSSOP-10 (DGS)
Best for	Precision, slow signals	Faster, coarser signals

The counterintuitive part: more bits do not automatically mean a better reading. The ADS1115’s quantization floor is tiny, but your layout noise usually dominates long before bit 16. If you put a noisy switching regulator next to the analog inputs, you will measure the noise with beautiful 16-bit precision. Resolution you cannot use is resolution you paid for and threw away.

ADS1115IDGSR VSSOP (DGS) Package and SMT Assembly Notes

The DGS suffix is a 10-pin VSSOP: a 3.0 mm × 3.0 mm body on 0.5 mm pin pitch, gull-wing leads, MSL-2 moisture sensitivity. It is a clean part to place, but the 0.5 mm pitch means stencil and paste discipline decide your yield.

For SMT assembly, a 0.1 mm (4 mil) laser-cut stainless stencil with a 1:1 aperture works well; drop to 0.12 mm only if you also see insufficient paste on neighboring larger parts on the same panel. Reflow to a standard lead-free SAC305 profile with peak 245–250 °C, and keep time-above-liquidus in the 60–90 s window. Class 2 acceptance per IPC-A-610 covers most commercial builds; demand Class 3 only if the board ships into automotive or medical.

A real-world case: a sensor-node client reflowed ADS1115IDGSR parts on a panel shared with bulky 1206 caps and used one global profile. The big caps shadowed the small VSSOP, the converter ran cold, and ~3% showed marginal head/heel fillets that AOI flagged later as intermittent opens in the field. The fix was not a hotter oven — it was panel DFM review and rebalancing thermal mass across the array. Mixed-mass panels are a DFM problem, not a profile problem.

Reading the device after assembly is cheap insurance. Add a Functional/AOI check that simply reads register 0x00 back at a known input; a wrong I2C address or a tombstoned decoupling cap shows up instantly.

Common ADS1115IDGSR Design and Assembly Mistakes to Avoid

Send this section to a junior engineer before they spin the board. Most ADS1115IDGSR failures are not silicon — they are layout and handling.

1. Treating ±6.144 V as an input rating. It is a coding range; the absolute max at any pin is VDD + 0.3 V. Add input clamp/series resistors if your source can swing past the rail.
2. Skipping or undersizing decoupling. Place a 0.1 µF X7R right at the VDD pin with a short return; a noisy supply shows up as LSB chatter you will blame on the sensor.
3. Sharing the analog return with switching-current ground. Give AIN returns a quiet path back to the ADC; do not route them across a buck regulator’s loop.
4. Leaving the ADDR pin floating or marginally biased — you get an unstable I2C address. Tie it hard to GND/VDD/SDA/SCL.
5. Wrong pull-up values for the bus speed and load, so 400 kHz transactions intermittently fail the rise-time spec.
6. Ignoring MSL-2 handling. An unbaked, long-opened reel risks popcorning at reflow; follow J-STD-033 floor-life rules.
7. Forgetting the converter is ratiometric to the on-chip reference, then expecting an external precision reference to improve absolute accuracy — it will not, because the device does not use one.

Do-It-Monday: ADS1115IDGSR Action Checklist

• Recompute your LSB at the PGA setting you actually plan to use, and confirm it beats your sensor’s noise floor — otherwise step the gain up.
• Drop a 0.1 µF X7R at VDD and a dedicated quiet analog return on this revision of the layout.
• Lock the ADDR strap and the I2C pull-up values for your target bus speed before layout freeze.
• On your BOM line, specify sealed MSL-2 reel and an acceptable date-code window to avoid resold, re-baked stock.
• Add a post-reflow register read-back as a functional test step so a bad joint or wrong address is caught at the line, not in the field.

Frequently Asked Questions About the ADS1115IDGSR

What package is the ADS1115IDGSR?

It is a 10-pin VSSOP, denoted by the DGS suffix — a 3.0 mm × 3.0 mm gull-wing SMD body on 0.5 mm pin pitch, rated MSL-2. The fine pitch is easily handled by standard SMT lines with a 4 mil laser-cut stencil and SAC305 reflow.

What is the difference between ADS1115 and ADS1015?

The ADS1115 is 16-bit at up to 860 SPS; the ADS1015 is 12-bit at up to 3,300 SPS. They are pin- and register-compatible. Choose the ADS1115 for precision on slow signals, the ADS1015 when you need faster, coarser sampling.

How many ADS1115IDGSR devices can share one I2C bus?

Up to four. A single ADDR pin selects addresses 0x48, 0x49, 0x4A, or 0x4B by tying it to GND, VDD, SDA, or SCL. Four devices give you 16 single-ended channels on one two-wire bus.

What is the ADS1115 maximum input voltage?

The absolute maximum at any analog input is VDD + 0.3 V, regardless of the PGA setting. The ±6.144 V option is a digital coding range, not an input rating — on a 3.3 V supply your real input ceiling is about 3.6 V.

Does the ADS1115IDGSR need an external voltage reference?

No. It has an internal low-drift reference, and the conversion is ratiometric to it. Adding an external reference does not improve absolute accuracy because the device does not use one; spend that effort on clean supply decoupling and layout instead.

What sample rates does the ADS1115 support?

Eight programmable data rates from 8 SPS up to 860 SPS. Lower rates average more and reduce noise; higher rates trade some effective resolution for throughput. Pick the slowest rate your application loop can tolerate for the quietest readings.

Sourcing the ADS1115IDGSR With Confidence

The ADS1115IDGSR earns its place because it turns a pin-starved measurement problem into four addressable, 16-bit channels on two wires — provided you respect the input limits, decouple it properly, and treat the VSSOP package as the fine-pitch part it is. Get those right and it is one of the most forgiving precision ADCs on the market.

Building a board around the ADS1115IDGSR? Send your Gerber and BOM for a free DFM review and a same-day quote on fab plus assembly.

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Reference

Texas Instruments ADS1115 product datasheet — ti.com/product/ADS1115