Texas Instruments Clocks & Timing: Oscillators & Jitter Cleaners

A Texas Instruments clock generator, oscillator, buffer or jitter cleaner sets and distributes the timing reference every digital and mixed-signal board depends on. TI’s clocks-and-timing line spans programmable oscillators, clock generators, fanout buffers, ultra-low-noise jitter cleaners and real-time clocks. This guide explains where each fits, puts real part numbers against their jitter specs, and covers the controlled-impedance layout that separates a clean clock tree from a noisy one.

The single most important idea in clocking is that jitter, not frequency, is usually what limits a high-performance system. Get the clock right and the converters and links behave; get it wrong and no amount of downstream effort recovers the lost performance.

• Jitter cleaners: the LMK04832 is an ultra-low-noise dual-loop device with 15 outputs and JESD204B SYSREF for up to 7 converters.
• Programmable oscillators: the LMK61E2 replaces a fixed crystal oscillator with a configurable, ultra-low-jitter source.
• Clock generators and buffers: parts like the CDCE6214 generate and fan out multiple clock domains from one reference.
• Clock jitter sets the SNR ceiling of a fast ADC — a few hundred femtoseconds at a high input frequency caps your effective bits.

What TI Clock and Timing Devices Do

A timing tree starts with a reference — a crystal, a crystal oscillator (XO) or a temperature-compensated oscillator — and turns it into the exact frequencies and clean edges the rest of the board needs. TI’s portfolio breaks into oscillators (the source), clock generators (synthesise new frequencies via a PLL), clock buffers (fan one clock out to many loads), jitter cleaners (lock to a noisy input and regenerate a low-jitter output), real-time clocks (keep wall-clock time), and delay lines (trim skew).

The decision usually comes down to how much phase noise the most sensitive load can tolerate. A microcontroller is forgiving; a 14-bit, high-speed ADC sampling a high-IF signal is not.

How to Choose a TI Clock: Jitter, Outputs and Architecture

Need	TI device class	Representative part	Why
Clean clocks for converters	Jitter cleaner	LMK04832	Dual-loop PLL, 15 outputs, JESD204B SYSREF, holdover
Replace a fixed XO	Programmable oscillator	LMK61E2	Ultra-low-jitter, configurable frequency
Fan one clock to many loads	Clock buffer / generator	CDCE6214	Multiple outputs from one reference
Keep time when powered down	Real-time clock	BQ32002	I²C RTC with battery backup

Two non-obvious points decide most clocking outcomes. First, the LMK04832’s value is not its frequency range but its output format and SYSREF support: its 14 outputs can be set to LVDS, LVPECL, LVCMOS or CML, and it delivers the deterministic SYSREF that JESD204B converters need to align. Second, a “good enough” crystal can still fail the design — not from jitter but from a load-capacitance mismatch that pulls the frequency off target. The crystal datasheet’s load-cap spec must match the oscillator circuit, or the part runs at the wrong frequency even though it looks healthy.

Why Clock Jitter Limits Data Converters and RF Links

For a high-speed ADC, the achievable signal-to-noise ratio from jitter alone is set by the input frequency and the clock’s rms jitter — higher frequency and more jitter both push SNR down. At a high intermediate frequency, a clock with a few hundred femtoseconds of jitter can cost several effective bits, which is why a converter that looks perfect on paper underperforms when clocked from a noisy CMOS buffer. The fix is a jitter cleaner with low-noise differential outputs, often locked to a clean voltage-controlled crystal oscillator.

This is the link between clocking and the rest of the signal chain. Clean clocks feed Texas Instruments data converters (though the converter section lives under data converters), and the same low-jitter references serve Texas Instruments wireless connectivity radios and high-speed TI interface ICs such as SerDes and JESD204 links.

Clock Layout: Controlled Impedance and Crystal Placement

A clean clock IC on a sloppy layout gives a noisy clock. The rules that matter:

1. Treat clock lines as controlled-impedance transmission lines — 50 ohms single-ended, 100 ohms differential — routed per the IPC-2221 geometry guidance, kept short, with no stubs and minimal vias.
2. Route differential clocks (LVDS, LVPECL) as tight, length-matched pairs and keep them away from switching power and digital noise.
3. Lay out the crystal with short traces, a ground guard and a clean reference under it; honour the load-capacitance specification exactly.
4. Place series-termination resistors at the source for single-ended CMOS clocks to control reflections and ringing.

A communications client measured an ADC SNR about 6 dB below the datasheet. The converter and board layout looked fine; the culprit was clock jitter from a general-purpose CMOS buffer feeding the sample clock. Replacing it with a low-noise jitter cleaner driving LVPECL outputs recovered the missing SNR. Nothing in the data path changed — only the clock.

Building a Clock Tree: Reference, Generation and Distribution

A clock tree is built in three layers, and TI has a device class for each. The reference layer is the source — a crystal, a crystal oscillator, or a programmable oscillator such as the LMK61E2 that replaces a fixed-frequency can with a configurable, ultra-low-jitter part. The generation layer synthesises the exact frequencies the system needs from that reference, using a clock generator or a PLL. The distribution layer fans those clocks out to every load with a buffer, preserving edge quality along the way.

Where performance is critical, a jitter cleaner sits between layers: it locks to a noisy or low-quality input and regenerates a clean output, often using an external voltage-controlled crystal oscillator for the lowest phase noise. The LMK04832 combines generation, cleaning and distribution in one device, driving up to fifteen outputs in formats from LVCMOS to LVPECL and CML, with holdover that keeps the outputs running if the reference disappears.

• Reference — crystal, XO, or programmable oscillator (LMK61E2) sets the base frequency and base jitter.
• Generation — a clock generator or PLL synthesises the system frequencies from the reference.
• Distribution — a fanout buffer copies one clean clock to many loads without adding meaningful jitter.

The architectural decision that matters most is integrated-VCO convenience versus external-VCXO performance. An RF synthesizer or generator with an internal voltage-controlled oscillator is compact and simple to design, but a jitter cleaner driving an external high-quality crystal oscillator achieves lower phase noise. Demanding converter and radio clocks justify the external oscillator; most digital domains do not.

Common TI Clock and Timing Mistakes

1. Clocking a high-speed converter from a noisy CMOS buffer and losing effective bits to jitter.
2. Mismatching the crystal load capacitance, which pulls the frequency off target.
3. Routing clocks as ordinary traces with stubs and vias, causing reflections.
4. Forgetting SYSREF distribution in a JESD204B system, so converters never align.
5. Fanning out a clock with a part whose additive jitter swamps the source.

Frequently Asked Questions About TI Clocks and Timing

What is a clock jitter cleaner?

A jitter cleaner locks a PLL to a noisy input clock and regenerates a much cleaner output, removing phase noise. TI’s LMK04832 is a dual-loop example with 15 outputs and JESD204B support for clocking high-speed converters.

What is the difference between a clock generator and a clock buffer?

A clock generator synthesises new frequencies from a reference using a PLL; a clock buffer simply fans one clock out to several loads without changing its frequency. Many designs use both — a generator to create the domains and buffers to distribute them.

Why does clock jitter matter for an ADC?

Sampling jitter adds uncertainty to when each sample is taken, which limits the signal-to-noise ratio, more so at high input frequencies. A few hundred femtoseconds of jitter can cost a high-speed converter several effective bits, so a low-jitter clock is essential.

What is SYSREF in JESD204B?

SYSREF is a timing-alignment signal that lets multiple JESD204B converters and the processor establish deterministic latency. A clock device like the LMK04832 generates SYSREF along with the device clocks so the converters sample in a known, repeatable relationship.

Do I need a TCXO or a simple crystal?

It depends on frequency stability over temperature. A plain crystal drifts with temperature; a temperature-compensated oscillator (TCXO) holds a tighter frequency. Wireless and timing-critical systems usually need the TCXO; many digital systems do not.

What does a clock buffer add to a design?

A clock buffer fans a single clean clock out to several loads while preserving its frequency and edge quality, and it isolates the source from load capacitance and reflections. The key specification is additive jitter — a poor buffer can degrade an otherwise clean clock, so the buffer’s own jitter must be well below the source’s.

What is clock holdover?

Holdover keeps a clock device’s outputs running at close to the right frequency when the input reference is lost, drawing on the last known state until a valid reference returns. The LMK04832 supports holdover, which matters in communications and timing systems that must not lose their clock during a reference glitch.

Design a Clean TI Clock Tree

Pick the timing device from the jitter your most sensitive load can tolerate, then route the clocks as controlled-impedance lines. Send your Gerber and BOM for a DFM review so impedance, crystal placement and termination are verified before the first build, and use the Texas Instruments component hub and TI logic and voltage-translation ICs to complete the digital section.