Xilinx Zynq-7000 SoC: ARM + FPGA Complete Beginner Guide

If you’ve been designing embedded systems for any length of time, you’ve probably hit that wall where a standalone microcontroller just doesn’t cut it anymore. Maybe you need real-time signal processing alongside your control logic, or perhaps your image processing pipeline demands hardware acceleration that software alone can’t deliver. That’s exactly where the Xilinx Zynq-7000 SoC enters the picture, and honestly, it changed how I approach complex embedded designs.

The Zynq platform represents something genuinely different in the embedded world. Rather than bolting an FPGA next to a processor on your PCB (with all the routing headaches that entails), AMD/Xilinx put both on the same silicon. The result? A Zynq SoC that lets you run Linux on dual ARM Cortex-A9 cores while simultaneously implementing custom hardware accelerators in programmable logic, all communicating through on-chip interconnects with bandwidth that would be impossible to achieve across a PCB.

In this guide, I’ll walk you through everything you need to know about the Zynq 7000 family, from architecture fundamentals to selecting development boards and understanding what it takes to design a custom PCB around these devices.

What is Xilinx Zynq-7000 SoC?

The Xilinx Zynq-7000 SoC (now under AMD following their acquisition) is a true System-on-Chip that integrates a feature-rich dual-core or single-core ARM Cortex-A9 Processing System (PS) with AMD’s 7-series programmable logic (PL) on a single device. This isn’t just an FPGA with a soft processor instantiated in fabric, the ARM cores are hardened silicon with dedicated cache, memory controllers, and peripherals.

What makes the Zynq 7000 SoC architecture compelling is the tight integration between the PS and PL sections. Over 3,000 interconnects link these domains, providing up to 100 Gb/s of on-chip bandwidth. That’s an order of magnitude better than what you’d achieve routing signals between discrete components on a PCB, and it fundamentally changes what’s possible in terms of hardware/software partitioning.

Key Differentiators of Zynq Architecture

The Zynq SoC approach differs from traditional FPGA designs in several important ways:

Processing System Always Boots First: Unlike pure FPGAs where you’re configuring the entire device from external flash, the Zynq-7000 PS boots from its internal BootROM and can run standalone without ever touching the programmable logic. This means you can develop and debug software while your hardware engineer is still working on the PL design.

Hardened Peripherals: USB, Ethernet, UART, SPI, I2C, CAN, GPIO, and DDR memory controllers are all implemented in dedicated silicon within the PS. You’re not burning FPGA resources on these standard interfaces.

Flexible Power Domains: The PS and PL sit on separate power domains. You can literally power down the FPGA fabric entirely while the ARM cores continue running, which is huge for power-sensitive applications.

Zynq 7000 Architecture Deep Dive

Understanding the Zynq 7000 architecture is essential before you start designing. Let me break down the major blocks.

Processing System (PS) Components

The PS in Xilinx Zynq devices contains:

Application Processing Unit (APU): Dual ARM Cortex-A9 MPCore processors running at up to 1 GHz (device dependent). Each core includes:

• 32 KB L1 instruction cache
• 32 KB L1 data cache
• 512 KB shared L2 cache
• NEON media processing engine for SIMD operations
• Hardware floating-point units

Memory Interfaces:

• DDR3/DDR3L/DDR2/LPDDR2 memory controller supporting up to 1 GB address space
• 256 KB On-Chip Memory (OCM) for low-latency access
• Quad-SPI flash controller
• NAND flash controller
• Static memory controller for NOR flash and SRAM

Peripheral Controllers: Two USB 2.0 OTG controllers, two Gigabit Ethernet MACs, two SD/SDIO controllers, two full CAN 2.0B controllers, two SPI controllers, two I2C controllers, two UARTs, up to 54 GPIO on MIO pins.

Programmable Logic (PL) Resources

The PL portion uses AMD’s 7-series FPGA architecture (Artix-7 or Kintex-7 class depending on the device variant). Available resources include:

Device	Logic Cells	Block RAM	DSP Slices	Max I/O	Transceivers
Z-7007S	23K	1.8 Mb	66	100	0
Z-7010	28K	2.1 Mb	80	100	0
Z-7012S	55K	2.5 Mb	120	150	4
Z-7014S	65K	3.8 Mb	170	200	0
Z-7015	74K	3.3 Mb	160	150	4
Z-7020	85K	4.9 Mb	220	200	0
Z-7030	125K	9.3 Mb	400	250	4
Z-7035	275K	17.6 Mb	900	362	8
Z-7045	350K	19.1 Mb	900	362	8
Z-7100	444K	26.5 Mb	2,020	400	16

The “S” suffix devices (Z-7007S, Z-7012S, Z-7014S) are single-core variants designed for cost-sensitive applications while maintaining the Zynq platform’s fundamental capabilities.

Read more Xilinx FPGA Series:

PS-PL Interconnects

The interface between PS and PL is where the Zynq-7000 SoC architecture really shines. Available interconnect ports include:

High-Performance AXI Ports (HP0-HP3): Four 64-bit or 32-bit slave interfaces providing PL masters direct access to DDR and OCM memory. These are your workhorses for high-bandwidth data movement.

Accelerator Coherency Port (ACP): 64-bit slave interface providing cache-coherent access from PL to the ARM memory system. Essential when your hardware accelerators need to share data structures with software without explicit cache management.

General Purpose Ports (GP0-GP1): Two 32-bit master interfaces and two 32-bit slave interfaces for lower-bandwidth control plane traffic.

Zynq 7000 Development Boards Comparison

Choosing the right development board is crucial for prototyping Zynq designs. Here’s a comparison of popular options:

Board	Zynq Device	Price Range	Key Features	Best For
PYNQ-Z2	XC7Z020	~$200	Python productivity, audio, HDMI, Arduino headers	Education, rapid prototyping
Arty Z7-20	XC7Z020	~$199	Compact, Pmod connectors, HDMI	Cost-effective development
ZedBoard	XC7Z020	~$400	FMC, OLED, audio, VGA/HDMI	All-around development
Zybo Z7-20	XC7Z020	~$299	MIPI CSI-2 Pcam, HDMI in/out	Embedded vision
ZC702	XC7Z020	~$900	FMC HPC/LPC, PCIe, extensive I/O	Production-ready prototyping
ZC706	XC7Z045	~$2,500	High-end device, GTX transceivers	High-performance applications
MicroZed	XC7Z010/020	~$178	SoM format, carrier boards available	Custom carrier development

Selecting Your First Zynq Board

For beginners, I typically recommend starting with either the PYNQ-Z2 or Arty Z7. The PYNQ platform adds a Python-based productivity layer that lets you experiment with hardware/software integration without immediately diving into HDL. You can literally control FPGA overlays from Jupyter notebooks, which dramatically flattens the learning curve.

If you’re more comfortable with traditional FPGA workflows and want maximum flexibility, the ZedBoard remains an excellent choice despite being an older design. The dual FMC connectors and extensive peripheral complement give you room to explore virtually any application domain.

For engineers evaluating Zynq for a production design, the official ZC702 evaluation kit makes sense despite its higher cost. It’s the reference platform Xilinx/AMD uses for their documentation and example designs, so you’ll encounter fewer compatibility issues working through tutorials.

Understanding the Zynq Boot Process

One aspect of the Zynq-7000 SoC that trips up many newcomers is the boot sequence. Unlike pure FPGAs where configuration happens through dedicated pins, the Zynq follows a processor-centric boot model.

Boot Sequence Overview

The boot process follows these stages:

Stage 0 – BootROM: Upon power-up or reset, the internal BootROM executes on CPU 0 while CPU 1 enters a wait-for-event state. The BootROM reads boot mode pins to determine the primary boot device (QSPI, SD, NAND, NOR, or JTAG), then copies the First Stage Bootloader to On-Chip Memory.

Stage 1 – FSBL: The First Stage Bootloader handles critical system initialization:

• PS clock configuration and PLL setup
• DDR memory controller initialization
• FPGA bitstream programming (optional)
• Loading and handoff to second stage (U-Boot or application)

Stage 2 – U-Boot or Application: For Linux systems, U-Boot typically loads the kernel, device tree, and root filesystem. For bare-metal applications, your code takes over directly from FSBL.

Boot Mode Selection

The Zynq determines boot source through dedicated mode pins sampled at reset:

Boot Mode	MIO[5:2]	Description
JTAG	0000	Development/debug mode
Quad-SPI	0001	QSPI flash boot (most common)
NAND	0010	NAND flash boot
NOR	0100	Parallel NOR flash
SD Card	0101	SD/SDIO boot

Most development boards use DIP switches or jumpers to select boot mode, making it easy to switch between SD card (for development) and QSPI (for production).

Creating Boot Images

The Vivado/Vitis toolchain generates BOOT.BIN files that package FSBL, bitstream, and application code. A typical boot image for a Linux system includes:

1. FSBL.elf – First Stage Bootloader
2. design_wrapper.bit – FPGA bitstream (optional)
3. u-boot.elf – Second stage bootloader
4. system.dtb – Device tree blob
5. image.ub – Linux kernel and initramfs

The bootgen utility stitches these components according to a BIF (Boot Image Format) specification file.

Real-World Applications for Zynq SoC

The Xilinx Zynq 7000 family has found its way into an impressive range of applications. Here’s where I’ve seen these devices deployed successfully:

Industrial Motor Control and Automation

The combination of real-time processing capability and reconfigurable I/O makes Zynq ideal for motor control applications. You can implement multiple PWM channels with precise timing in the PL while running higher-level motion planning algorithms on the ARM cores. The hardened CAN controllers handle industrial networking without consuming FPGA resources.

Embedded Vision Systems

Multi-camera driver assistance systems and industrial inspection equipment benefit enormously from the Zynq-7000 SoC architecture. Image sensor interfaces and pixel processing pipelines run in the PL at wire speed, while the PS handles object detection algorithms, system management, and network communication.

Software-Defined Radio

The Zynq platform has become a go-to choice for SDR implementations. ADC/DAC interfaces and baseband processing live in the PL, ARM cores handle protocol stacks and user interfaces, and the high-bandwidth PS-PL interconnects keep data flowing.

Test and Measurement

Companies like Tektronix use Zynq 7000 devices in their test equipment. The FPGA fabric handles high-speed signal acquisition and triggering while the processor system runs analysis software and user interfaces.

Medical Imaging

Ultrasound systems, endoscopes, and other medical imaging equipment leverage Zynq SoC for real-time image processing and display.

Read more Xilinx Products:

Common Challenges and How to Overcome Them

Based on years of working with the Zynq platform, here are the issues that catch people most often:

Challenge 1: PS-PL Clock Domain Crossing

When passing data between PS software and PL hardware, clock domain mismatches can cause subtle bugs. The PS operates on its own clock tree while PL can use completely different clock frequencies. Always use proper synchronization primitives (FIFOs, CDC cells) at the PS-PL boundary.

Challenge 2: AXI Protocol Errors

AXI is more complex than simpler bus protocols. Common mistakes include:

• Not properly handling BRESP/RRESP signals
• Violating transaction ordering requirements
• Incorrect burst length or size encoding
• Failing to complete transactions properly

The AXI Verification IP (VIP) available in Vivado can help debug protocol violations during simulation.

Challenge 3: DDR Calibration Failures

If DDR fails to calibrate during boot, your board won’t work. Common causes include:

• Incorrect termination resistor values
• Excessive length mismatch between signals
• Power supply noise affecting Vref
• Incorrect ODT settings in PS configuration

The Vivado Memory Interface Generator provides calibration status registers you can read via JTAG to diagnose failures.

Challenge 4: Linux Driver Development

Writing Linux drivers for PL peripherals requires understanding both the Linux driver model and your hardware interface. For simple register-based peripherals, the UIO (Userspace I/O) framework provides an easier path than kernel-space drivers. Reserve the complexity of proper kernel drivers for high-performance applications requiring interrupt handling or DMA.

Challenge 5: Debugging Hardware/Software Interactions

When issues span the PS-PL boundary, debugging becomes tricky. Helpful techniques include:

• ILA (Integrated Logic Analyzer) cores in PL to capture hardware signals
• System ILA for monitoring AXI transactions
• ARM DS-5 or Vitis debugger for software debugging
• Printf debugging via UART for quick checks
• Hardware breakpoints in processor debug mode

Getting Started with Zynq Development

The Xilinx Zynq development ecosystem centers around a few key tools:

Vivado Design Suite

Vivado handles all hardware aspects of Zynq design, including PS configuration, PL logic design, synthesis, implementation, and bitstream generation. The free WebPACK license covers smaller devices including the popular XC7Z010 and XC7Z020 used in most development boards.

The IP Integrator (IPI) block design flow is particularly relevant for Zynq-7000 development. You instantiate the ZYNQ7 Processing System IP block, configure it for your target board, and connect custom PL logic through the AXI interfaces.

Vitis Unified Software Platform

Vitis replaced the older Xilinx SDK and handles software development for the ARM cores. It includes bare-metal drivers for all PS peripherals, a first-stage bootloader (FSBL) generator, and debugging capabilities. You can target standalone (bare-metal), FreeRTOS, or Linux applications.

PetaLinux Tools

For Linux-based Zynq designs, PetaLinux provides a complete build system based on Yocto/OpenEmbedded. It generates bootloaders, kernel images, device trees, and root filesystems configured for Xilinx devices. Board Support Packages (BSPs) for official development boards simplify initial bring-up.

Development Workflow

A typical Zynq 7000 development workflow looks like:

1. Hardware Design in Vivado: Configure PS peripherals, design PL logic, establish PS-PL connections
2. Export Hardware: Generate XSA file containing hardware description
3. Software Development in Vitis: Create platform project from XSA, develop application software
4. System Integration: Generate boot images, test on hardware
5. Linux Development (if applicable): Build custom Linux distribution with PetaLinux

Step-by-Step First Project

Let me walk through creating your first Zynq project, as this practical knowledge is invaluable:

Creating the Hardware Design:

1. Launch Vivado and create a new RTL project targeting your board
2. Create a new Block Design using IP Integrator
3. Add the ZYNQ7 Processing System IP to the block design
4. Run Block Automation to configure PS for your target board preset
5. Double-click the PS block to customize peripherals (enable UART, GPIO, etc.)
6. Connect any PL logic to appropriate AXI interfaces
7. Validate design, create HDL wrapper, run synthesis and implementation
8. Export hardware including bitstream (File → Export → Export Hardware)

Creating the Software Application:

1. Launch Vitis and select your workspace directory
2. Create new Platform Project using exported XSA file
3. Build the platform to generate BSP and FSBL
4. Create new Application Project (Hello World is a good start)
5. Select your platform and target processor (ps7_cortexa9_0)
6. Build and debug using JTAG connection

The whole process takes maybe 30 minutes once you’re familiar with the tools. The first time through, budget a few hours for exploration and troubleshooting.

Understanding the PS-PL Interface in Practice

Working with the PS-PL interface is where Zynq really shines. Here’s how to think about the different connection options:

AXI GP (General Purpose) Ports: Use these for register-based control of PL peripherals. Memory-mapped registers let your ARM code configure and communicate with custom hardware blocks. Data rates are adequate for control traffic but not optimal for bulk transfers.

AXI HP (High Performance) Ports: When your PL logic needs to move large amounts of data to or from DDR memory, HP ports are your workhorses. They support burst transactions and provide direct memory access without passing through the CPU.

AXI ACP (Accelerator Coherency Port): This specialized port maintains cache coherency between PL and PS. Use it when PL-side accelerators need to share data structures with software without explicit cache flush/invalidate operations. The tradeoff is potentially higher latency compared to HP ports.

PCB Design Considerations for Zynq-7000

Having designed several custom boards around Zynq devices, here are the critical considerations:

Power Distribution System

The Zynq-7000 SoC requires multiple power rails with specific sequencing requirements:

Supply Rail	Typical Voltage	Description
VCCINT	1.0V	Core logic (PS and PL)
VCCAUX	1.8V	Auxiliary circuits
VCCBRAM	1.0V	Block RAM
VCCO_MIO	1.8V/2.5V/3.3V	PS MIO bank power
VCCO_PLx	1.2V-3.3V	PL I/O bank power
VCCPLL	1.8V	PLL power
PS_DDR	Device dependent	DDR interface power

Power sequencing follows a specific order: VCCINT must be stable before VCCAUX, and both must be valid before VCCO rails. The AMD Power Design Manager (XPE) tool helps estimate power consumption and validate your power architecture.

Decoupling Strategy

Per AMD’s UG933 PCB Design Guide, Zynq devices require significant decoupling capacitance. The processing system alone needs multiple bulk capacitors (47µF-100µF) plus numerous 0.47µF and 4.7µF ceramics distributed across supply pins.

Key guidelines from my experience:

• Place 0402 ceramics as close to BGA balls as possible
• Use multiple vias per capacitor pad to reduce parasitic inductance
• Don’t skimp on the capacitor count, stability issues are extremely difficult to debug
• Keep power and ground planes as close to the device side of the PCB as practical

DDR3 Layout

The PS DDR interface requires careful impedance-controlled routing:

• Data signals: 40Ω single-ended
• Address/command: 40Ω
• Clock: 80Ω differential
• Match data byte group lengths within 5 mils
• Match address/command to clock within 25 mils

The Vivado Memory Interface Generator (MIG) can adjust timing parameters to compensate for moderate length mismatches, but you’re making calibration work harder than necessary.

High-Speed Signals

If you’re using FPGA transceivers (available on Z-7015, Z-7030, Z-7035, Z-7045, Z-7100), follow standard multi-gigabit design practices:

• AC coupling capacitors placed adjacent to transmit pins
• Continuous ground reference plane under differential pairs
• Via-in-pad with backdrilling for BGA fanout
• 85Ω differential impedance unless protocol specifies otherwise

Stack-up Recommendations

For a cost-effective 8-layer stack-up targeting Zynq-7000 designs, consider:

Layer	Function	Material
L1	Signals (component side)	Copper
L2	Ground plane	Copper
L3	Power plane (VCCINT)	Copper
L4	Signals	Copper
L5	Signals	Copper
L6	Power plane (multiple rails)	Copper
L7	Ground plane	Copper
L8	Signals (solder side)	Copper

Larger devices like the Z-7045 or Z-7100 in BGA packages typically warrant 10-12 layer boards for proper signal escape and power integrity. The smaller CLG400 package devices (Z-7010, Z-7020) are manageable on 6-layer boards with careful planning.

Thermal Management

Zynq devices can dissipate significant power depending on PL utilization and clock speeds. Plan thermal management early:

• Calculate expected power using AMD’s Power Design Manager (XPE)
• Ensure adequate copper pour area on top and bottom layers connected to device thermal pad
• Consider heat sink attachment for high-performance applications
• Industrial temperature variants (-40°C to +100°C) are available for demanding environments

A common mistake is underestimating PL power consumption during prototyping. Your final production design might use significantly more FPGA resources than early development, so design thermal capacity with growth margin.

Design Review Checklist

Before releasing your Zynq-7000 PCB design, verify:

• [ ] All power rails meet voltage tolerance specifications
• [ ] Power sequencing follows device requirements
• [ ] Decoupling capacitors meet quantity and placement guidelines per UG933
• [ ] DDR interface impedance and length matching within specifications
• [ ] Boot mode pins have proper pull-ups/pull-downs for intended configuration
• [ ] JTAG interface accessible for debug
• [ ] PS_CLK oscillator properly specified and routed
• [ ] Reset circuit meets minimum pulse width requirements
• [ ] Thermal solution adequate for worst-case power dissipation

Essential Resources and Downloads

Here are the critical documents and tools for Zynq-7000 development:

Official AMD Documentation

Document	Number	Description
Technical Reference Manual	UG585	Complete register-level description of all PS peripherals
Data Sheet Overview	DS190	Device features, block diagrams, general specifications
DC/AC Switching Characteristics	DS187/DS191	Timing specifications, operating conditions
PCB Design Guide	UG933	Power distribution, signal integrity, layout guidance
Software Developers Guide	UG821	Programming models, boot process, security

Download Links

• Vivado Design Suite: https://www.xilinx.com/support/download.html
• PetaLinux Tools: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html
• Zynq-7000 Documentation: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM
• The Zynq Book (Free PDF): https://www.zynqbook.com/
• AMD Wiki Getting Started: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/189530183/Zynq-7000

Community Resources

• AMD Community Forums: Active community support for Zynq development questions
• Digilent Forum: Board-specific discussions for Digilent Zynq boards
• GitHub: Numerous open-source Zynq projects and reference designs

Zynq vs. Zynq UltraScale+ — When to Upgrade

The Zynq-7000 family remains excellent for many applications, but AMD’s newer Zynq UltraScale+ MPSoC offers significant improvements:

Feature	Zynq-7000	Zynq UltraScale+
Application Processor	Dual Cortex-A9 @ 1 GHz	Quad Cortex-A53 @ 1.5 GHz
Real-time Processor	None	Dual Cortex-R5
GPU	None	Mali-400 MP2
FPGA Fabric	7-series (28nm)	UltraScale (16nm)
Max Transceivers	16	16 (GTH 16.3 Gb/s)
Security	AES-256, SHA	Enhanced with PUF

For new designs with demanding performance requirements, the UltraScale+ family is worth evaluating. However, Zynq-7000 remains more cost-effective for volume production and has a larger ecosystem of reference designs and community support.

Frequently Asked Questions

Can I run Linux on Zynq-7000?

Yes, running Linux on Zynq is fully supported and quite common. The dual Cortex-A9 cores with MMU are well-suited for Linux. PetaLinux tools provide a straightforward path to building custom Linux distributions, and you can boot from SD card, QSPI flash, or NAND. The PL remains fully functional while Linux runs on the PS, allowing hardware accelerators to work alongside software applications.

What’s the difference between Zynq-7000 and Zynq-7000S?

The Zynq-7000S variants (Z-7007S, Z-7012S, Z-7014S) feature single-core ARM Cortex-A9 processors instead of dual-core. They’re optimized for cost-sensitive applications where the second CPU core isn’t needed. The PL resources and PS peripherals remain comparable to their dual-core counterparts, making them excellent choices for motor control, industrial IoT, and embedded vision applications where software requirements are modest.

How much does Zynq development cost to get started?

You can start Zynq development for under $200 with boards like the Arty Z7 or PYNQ-Z2. The Vivado WebPACK license is free and covers these devices. If your application requires larger devices like the Z-7030 or Z-7045, you’ll need a paid Vivado license and higher-cost development hardware. Total cost of entry compares favorably to many competing platforms.

Can Zynq-7000 boot without programming the FPGA?

Yes, absolutely. The Zynq-7000 PS boots from internal BootROM and can execute software entirely independent of the PL. You can develop and test ARM software without having any FPGA bitstream. The PL only needs programming when your application uses custom logic in the FPGA fabric or routes PS peripherals through EMIO pins to PL-side I/O.

What operating systems besides Linux run on Zynq?

The Zynq ARM cores support numerous operating systems including FreeRTOS (very popular for bare-metal RTOS applications), VxWorks, QNX, Android, and Windows Embedded Compact. For simple applications, standalone (no OS) development is also fully supported with Xilinx’s bare-metal drivers. The choice depends on your real-time requirements, software ecosystem needs, and licensing considerations.

Wrapping Up

The Xilinx Zynq-7000 SoC family represents a mature and well-supported platform for designs requiring both processor flexibility and FPGA-based hardware acceleration. After working with these devices across multiple projects, I can confidently say the architecture delivers on its promise of simplifying complex embedded systems.

Whether you’re building industrial automation equipment, embedded vision systems, or custom test instruments, the Zynq platform gives you the tools to partition your design optimally between hardware and software. The learning curve is real, especially if you’re coming from a pure software or pure FPGA background, but the documentation and community resources have never been better.

Start with a development board, work through the official tutorials, and don’t hesitate to leverage the extensive example designs. The investment in learning this platform pays dividends across a remarkably wide range of applications.