Zynq UltraScale+ MPSoC: Next-Gen ARM + FPGA Platform Guide

The Zynq UltraScale+ represents a fundamental shift in embedded system architecture. After working with multiple generations of Xilinx SoCs, I can say this platform delivers capabilities that simply weren’t possible five years ago—64-bit processing, hardware video codecs, integrated GPU, and massive programmable logic resources all on a single chip.

This comprehensive guide examines the Xilinx Zynq UltraScale+ architecture, device variants, development ecosystem, and practical applications. Whether you’re evaluating this platform for a new design or migrating from Zynq-7000, you’ll find the technical details needed to make informed decisions.

Understanding the Zynq UltraScale+ Architecture

The Zynq UltraScale+ FPGA architecture fundamentally differs from its Zynq-7000 predecessor through heterogeneous multiprocessing design. Rather than simply pairing a processor with FPGA fabric, AMD (formerly Xilinx) integrated multiple specialized processing engines optimized for different workloads.

Processing System Overview

The Processing System (PS) contains the application processors, real-time processors, and all peripheral interfaces. Unlike standalone processors or the original Zynq-7000, the UltraScale+ PS delivers 64-bit computing capability essential for modern applications.

The Application Processing Unit (APU) centers on ARM Cortex-A53 cores implementing the ARMv8-A architecture. These 64-bit cores run at up to 1.5 GHz and support hardware virtualization, asymmetric multiprocessing (AMP), symmetric multiprocessing (SMP), and ARM TrustZone security extensions. Depending on the device variant, you get either dual-core (CG devices) or quad-core (EG/EV devices) configurations.

The Real-time Processing Unit (RPU) provides dual ARM Cortex-R5F cores operating at up to 600 MHz. These cores handle deterministic, low-latency tasks that application processors can’t reliably service—motor control loops, safety monitoring, interrupt handling, and real-time I/O management. The RPU can operate in lockstep mode for safety-critical applications requiring redundancy.

Programmable Logic Capabilities

The Programmable Logic (PL) region contains UltraScale+ architecture FPGA fabric—not the 7-series fabric found in Zynq-7000. This distinction matters significantly for timing closure and resource efficiency.

Key PL improvements include:

• UltraRAM blocks: 288 Kb high-density memory blocks enabling large on-chip buffers without external SRAM
• Enhanced DSP slices: 27×18 multipliers with pre-adders and cascaded connections for efficient signal processing
• Improved CLB architecture: 8 LUTs and 16 flip-flops per CLB with better routing efficiency
• Higher I/O performance: Support for DDR4, LPDDR4, and multiple high-speed serial protocols

The PS-PL interface bandwidth deserves attention. The Zynq UltraScale+ provides over 150 Gbps of aggregate bandwidth between processing system and programmable logic through multiple AXI interface types—high-performance ports, accelerator coherency ports, and low-latency paths optimized for specific traffic patterns.

Zynq UltraScale+ Device Variants Explained

AMD offers three distinct Zynq UltraScale+ variant families, each targeting different application requirements. Selecting the appropriate variant significantly impacts both capability and cost.

CG Devices: Cost-Optimized Processing

CG (Cost-optimized Graphics-less) devices provide essential MPSoC functionality at the lowest price points. These devices include:

• Dual-core ARM Cortex-A53 at up to 1.3 GHz
• Dual-core ARM Cortex-R5 at up to 533 MHz
• 103K to 600K system logic cells
• No GPU or video codec

CG devices suit applications where processing requirements don’t justify quad-core CPUs or dedicated graphics hardware—industrial control systems, networking equipment, sensor fusion platforms, and cost-sensitive embedded designs.

EG Devices: Enhanced Graphics Processing

EG devices add quad-core processing and GPU acceleration for graphics-intensive applications:

• Quad-core ARM Cortex-A53 at up to 1.5 GHz
• Dual-core ARM Cortex-R5 at up to 600 MHz
• ARM Mali-400 MP2 GPU
• 103K to 1,143K system logic cells
• No hardware video codec

The Mali-400 MP2 GPU handles OpenGL ES 2.0 rendering for human-machine interfaces, instrument clusters, and display applications. EG devices target automotive infotainment, industrial HMI, medical displays, and aerospace situational awareness systems.

EV Devices: Video Codec Integration

EV devices include everything in EG devices plus a dedicated H.264/H.265 video codec unit (VCU):

• Quad-core ARM Cortex-A53 at up to 1.5 GHz
• Dual-core ARM Cortex-R5 at up to 600 MHz
• ARM Mali-400 MP2 GPU
• H.264/H.265 hardware codec (up to 4K60)
• 192K to 504K system logic cells

The VCU enables simultaneous encoding and decoding at resolutions up to 4K at 60 frames per second. This makes EV devices ideal for video surveillance, broadcast equipment, medical endoscopy, automotive ADAS cameras, and streaming applications.

Read more Xilinx FPGA Series:

Device Variant Comparison Table

Feature	CG Devices	EG Devices	EV Devices
Cortex-A53 Cores	2 (1.3 GHz)	4 (1.5 GHz)	4 (1.5 GHz)
Cortex-R5 Cores	2 (533 MHz)	2 (600 MHz)	2 (600 MHz)
Mali-400 GPU	No	Yes	Yes
Video Codec	No	No	H.264/H.265
Logic Cells	103K–600K	103K–1,143K	192K–504K
Target Applications	Industrial, IoT	Graphics, HMI	Video, Surveillance

Xilinx Zynq UltraScale+ Technical Specifications

Understanding the detailed specifications helps properly size devices for specific applications.

Processing System Specifications

Component	Specification
APU Architecture	ARM Cortex-A53 (ARMv8-A, 64-bit)
APU Frequency	Up to 1.5 GHz (EG/EV), 1.3 GHz (CG)
APU L1 Cache	32 KB I-cache + 32 KB D-cache per core
APU L2 Cache	1 MB shared
RPU Architecture	ARM Cortex-R5F (ARMv7-R, 32-bit)
RPU Frequency	Up to 600 MHz
RPU TCM	128 KB per core
On-Chip Memory	256 KB

Memory Interface Capabilities

Interface	Specification
PS DDR Controller	64-bit or 32-bit, ECC support
DDR4 Support	Up to 2400 MT/s
DDR3/DDR3L	Up to 2133 MT/s
LPDDR4	32-bit, up to 3200 MT/s
LPDDR3	Up to 1866 MT/s
PL DDR	Configurable via MIG

High-Speed Transceivers

The Zynq UltraScale+ includes three transceiver types for different bandwidth requirements:

Transceiver	Data Rate	Application
PS-GTR	1.25–6.0 Gb/s	USB 3.0, SATA, PCIe Gen2, DisplayPort
GTH	0.5–16.3 Gb/s	10G Ethernet, PCIe Gen3, high-speed serial
GTY	0.5–32.75 Gb/s	25G/100G Ethernet, PCIe Gen4, data center

The PS-GTR transceivers connect directly to the processing system for USB 3.0, SATA, PCIe, and DisplayPort interfaces. GTH and GTY transceivers reside in the programmable logic for custom protocols and higher bandwidth applications.

Peripheral Controllers

The processing system includes extensive peripheral support:

Peripheral	Count	Features
Gigabit Ethernet	4	IEEE 1588 PTP support
USB	2	USB 3.0 and USB 2.0
PCIe	2	Gen2 x4 or Gen1 x8
SATA	2	3.0 Gb/s
DisplayPort	1	Source, up to 4K
SD/SDIO	2	SD 3.0, eMMC 4.51
UART	2	Up to 1 Mb/s
SPI	2	Master/slave
I2C	2	Master/slave
CAN	2	CAN 2.0B
GPIO	78	MIO pins

Key Applications for Zynq UltraScale+ Platforms

The Xilinx Zynq UltraScale+ architecture enables applications across multiple industries. Understanding where this platform excels helps justify its complexity and cost versus simpler alternatives.

5G Wireless Infrastructure

5G base stations and radio units require massive parallel processing for beamforming, MIMO processing, and protocol handling. The UltraScale+ programmable logic handles baseband processing while ARM cores manage control plane functions and network protocols. High-speed transceivers connect to RF front-ends and backhaul networks.

The platform’s power management capabilities prove critical for radio equipment deployed in temperature-controlled enclosures with strict thermal budgets.

Automotive ADAS and Autonomous Driving

Advanced driver assistance systems demand real-time sensor fusion, computer vision, and decision-making capabilities. Automotive-qualified XA Zynq UltraScale+ devices meet AEC-Q100 specifications with ISO 26262 ASIL-C certification.

Applications include:

• Camera-based object detection and classification
• Radar and LiDAR point cloud processing
• Sensor fusion across multiple input types
• Path planning and decision support
• In-vehicle networking (Ethernet, CAN, FlexRay)

The EV variant’s video codec handles camera streams without consuming programmable logic resources, reserving FPGA fabric for custom image processing pipelines.

Industrial IoT and Automation

Factory automation systems benefit from the combination of real-time processing and network connectivity. The Cortex-R5 cores handle time-critical control loops while Cortex-A53 cores run industrial Ethernet stacks (EtherCAT, PROFINET, EtherNet/IP) and higher-level automation software.

The programmable logic implements custom motor control algorithms, high-speed data acquisition, and specialized industrial protocols not available in standard microcontrollers.

Medical Imaging and Endoscopy

Medical devices require deterministic timing, image processing capability, and regulatory compliance. The Zynq UltraScale+ EV devices handle endoscopy video encoding while programmable logic implements image enhancement algorithms—noise reduction, color correction, and feature detection.

The platform’s long lifecycle commitment (through 2045 for UltraScale+ devices) supports medical device lifecycles that often span decades.

Aerospace and Defense

Military and aerospace applications leverage the platform’s security features, radiation-tolerant variants, and processing density. Applications include radar processing, electronic warfare, secure communications, and flight control systems.

The ARM TrustZone and dedicated security unit enable secure boot, encrypted storage, and tamper detection required for classified systems.

Zynq UltraScale+ Development Boards and Pricing

AMD and third-party vendors offer evaluation kits ranging from affordable entry points to full-featured professional platforms.

Official AMD Evaluation Kits

Board	Device	Key Features	Approximate Price
ZCU102	XCZU9EG	Full-featured, dual FMC, comprehensive I/O	$2,995
ZCU104	XCZU7EV	Video-focused, MIPI, HDMI, DisplayPort	$1,555
ZCU106	XCZU7EV	Extended I/O, dual FMC HPC connectors	$3,570
Kria KV260	XCK26	Vision AI starter kit, compact	$199
Kria KR260	XCK26	Robotics starter kit	$349

Third-Party Development Boards

Board	Vendor	Device	Approximate Price
Genesys ZU-3EG	Digilent	XCZU3EG	$1,295
Genesys ZU-5EV	Digilent	XCZU5EV	$1,995
Ultra96-V2	Avnet	XCZU3EG	$249
PYNQ-ZU	TUL	XCZU5EG	$199
AXU3EG	Alinx	XCZU3EG	~$500

The Kria SOM (System-on-Module) platform deserves special attention. At $199 for the KV260 starter kit, it provides an accessible entry point for evaluating Zynq UltraScale+ capabilities without the $3,000+ investment of traditional evaluation kits.

Software Development Ecosystem

The Xilinx Zynq UltraScale+ software ecosystem spans hardware design tools, embedded software development, and operating system support.

Hardware Design Tools

Vivado Design Suite handles all FPGA development tasks—RTL synthesis, implementation, timing closure, and bitstream generation. The free Vivado ML Standard Edition (formerly WebPACK) supports smaller UltraScale+ devices, while larger devices require the paid edition.

Key Vivado features for MPSoC development:

• IP Integrator for graphical block design
• Zynq UltraScale+ MPSoC IP configuration wizard
• Integrated Logic Analyzer (ILA) for hardware debugging
• High-Level Synthesis (HLS) for C/C++ to RTL

Embedded Software Development

Vitis Unified Software Platform provides the IDE and toolchain for ARM software development. It includes:

• Eclipse-based IDE with cross-compiler toolchains
• Bare-metal and FreeRTOS application development
• Debug and profiling tools
• Hardware abstraction layer (HAL) libraries
• Platform and application project management

Linux Development

PetaLinux Tools simplify embedded Linux development for Zynq platforms:

• Board Support Package (BSP) generation
• Kernel and root filesystem customization
• Device tree generation and modification
• QEMU-based simulation
• SD card and boot image creation

The Linux kernel supports all PS peripherals plus many PL IP cores through mainline and AMD-maintained drivers.

Boot Process Understanding

The Zynq UltraScale+ boot process involves multiple stages:

1. Platform Management Unit (PMU) executes ROM code
2. First Stage Boot Loader (FSBL) initializes PS and loads PL bitstream
3. ARM Trusted Firmware (ATF) provides secure monitor services
4. U-Boot or custom bootloader loads operating system
5. Linux kernel or RTOS begins execution

Understanding this boot sequence proves essential when debugging startup issues or implementing secure boot.

Essential Resources for Zynq UltraScale+ Development

These resources support development across all Zynq UltraScale+ platforms.

Official AMD Documentation

Resource	Document Number	Description
MPSoC Overview	DS891	Device specifications and features
Technical Reference Manual	UG1085	Comprehensive architecture reference
Software Developer Guide	UG1137	Software development information
Register Reference	UG1087	Complete register definitions
PCB Design Guide	UG583	Board design guidelines

Download Links

Resource	URL
Vivado Design Suite	https://www.xilinx.com/support/download.html
Vitis Platform	https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html
PetaLinux Tools	https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html
Board Files	https://github.com/Xilinx/XilinxBoardStore
Reference Designs	https://github.com/Xilinx

Community and Support Resources

Resource	URL	Description
AMD Support Forums	https://support.xilinx.com	Official technical support
Xilinx Wiki	https://xilinx-wiki.atlassian.net	Community documentation
FPGA Developer	https://www.fpgadeveloper.com	Tutorials and examples
Digilent Forum	https://forum.digilent.com	Board-specific support
RidgeRun Wiki	https://developer.ridgerun.com	Multimedia development

Read more Xilinx Products:

Power Management Architecture

Effective power management separates successful Zynq UltraScale+ designs from problematic ones. The platform provides sophisticated power control that, when properly utilized, delivers substantial efficiency gains.

Power Domains and Islands

The UltraScale+ architecture divides the device into multiple power domains that can be independently controlled:

• Full Power Domain (FPD): Contains the APU, GPU, DisplayPort, SATA, PCIe, and high-speed interfaces
• Low Power Domain (LPD): Contains the RPU, USB, Ethernet, and low-speed peripherals
• PL Power Domain: The entire programmable logic region
• Battery Power Domain (BPD): Real-time clock and minimal keep-alive circuitry

Each domain supports independent power gating, allowing unused subsystems to be completely powered down. A design using only the RPU for real-time control can disable the entire FPD, reducing power consumption by 60% or more compared to running all processors.

Power States and Transitions

The platform supports multiple power states beyond simple on/off:

Power State	Active Components	Typical Power	Wake Time
Full Run	All domains active	5-15W	N/A
FPD Off	LPD + PL only	2-5W	~1ms
Deep Sleep	Minimal (BPD)	180 nW	~100ms
Power Off	None	0	Full boot

The Platform Management Unit (PMU) manages power state transitions automatically based on software configuration. Properly designed firmware can transition between states based on workload demands, thermal conditions, or external events.

Thermal Considerations

High-performance Zynq UltraScale+ designs generate significant heat. The ZCU102 evaluation board, for instance, includes an active fan and substantial heat sink for the XCZU9EG device. Production designs must carefully consider:

• Package thermal resistance (junction-to-case, junction-to-board)
• Airflow requirements for passive or active cooling
• Thermal throttling thresholds and behavior
• Operating temperature grades (commercial, industrial, extended)

The System Monitor (SYSMON) provides on-chip temperature and voltage monitoring. Proper designs implement thermal management software that reduces clock frequencies or shuts down non-essential functions when temperatures exceed safe limits.

Design Migration and Scalability

One significant advantage of the Xilinx Zynq UltraScale+ family is footprint compatibility across devices, enabling designs to scale up or down without PCB changes.

Package Compatibility

Devices sharing the same package footprint identifier (the last letter and number in the package designator) are footprint compatible. For example:

• XCZU3EG-SFVC784 and XCZU5EV-SFVC784 share the same footprint
• XCZU7EV-FFVB1156 and XCZU9EG-FFVB1156 share the same footprint

This compatibility allows designers to:

• Start development with lower-cost devices and migrate to larger devices for production
• Offer product variants using different devices on the same PCB
• Respond to supply chain issues by qualifying alternate devices
• Future-proof designs against changing requirements

Design Portability from Zynq-7000

Engineers migrating from Zynq-7000 will find the transition manageable but not trivial. Key differences requiring attention:

Software changes:

• 64-bit compiler toolchain required for APU code
• Different boot process with PMU and ATF stages
• Updated device tree structure and bindings
• New peripheral register maps

Hardware changes:

• Different power supply requirements and sequencing
• New high-speed interface protocols (DDR4, USB 3.0)
• Different I/O banking and voltage requirements
• Updated PCB design guidelines

FPGA fabric changes:

• Different primitives (UltraRAM, enhanced DSP)
• Improved timing characteristics but different constraints
• Updated IP core versions with new features
• Changed resource utilization for equivalent designs

Plan for a significant engineering investment when migrating existing Zynq-7000 designs, even when the logical functionality remains unchanged.

Security and Safety Features

Modern embedded systems require robust security and functional safety capabilities. The Zynq UltraScale+ architecture addresses both requirements comprehensively.

Security Architecture

The dedicated Configuration Security Unit (CSU) provides:

• Secure boot: RSA-4096 authentication, AES-256 encryption
• Key management: Secure key storage and derivation
• Anti-tamper: Physical and environmental attack detection
• TrustZone: ARM-standard security extensions
• Device attestation: Unique device identification

These features enable applications requiring military-grade security or protection against intellectual property theft.

Functional Safety Support

For safety-critical applications, AMD offers:

• ISO 26262 certification: ASIL-C level for automotive
• Lockstep RPU mode: Dual-core redundant execution
• ECC memory: Error detection and correction throughout
• Safety island: Isolated real-time processing domain
• Fault injection: Built-in test capabilities

The XA (automotive-qualified) variants meet AEC-Q100 specifications for automotive deployment.

Frequently Asked Questions

What is the difference between Zynq-7000 and Zynq UltraScale+?

The Zynq UltraScale+ represents a generational leap from Zynq-7000. Key differences include 64-bit ARM Cortex-A53 processors (versus 32-bit Cortex-A9), separate real-time Cortex-R5 cores, optional GPU and video codec, UltraScale+ FPGA fabric with UltraRAM, higher-speed transceivers, and advanced security features. The UltraScale+ typically delivers 2-5x better performance per watt for comparable applications.

Which Zynq UltraScale+ device should I choose for video processing?

For video applications requiring encoding or decoding, select EV devices with the integrated H.264/H.265 video codec. The ZU4EV, ZU5EV, and ZU7EV provide codec capability plus adequate programmable logic for video processing pipelines. If you only need video display without encoding, EG devices with the Mali GPU may suffice at lower cost.

Can I run Linux on Zynq UltraScale+?

Yes, Linux runs excellently on the Cortex-A53 APU. AMD provides PetaLinux tools for customized embedded Linux development, and mainstream Linux distributions support the platform. You can run 64-bit Ubuntu, Yocto-based distributions, or custom Linux builds. The Cortex-R5 RPU typically runs bare-metal code or an RTOS for real-time tasks alongside Linux on the APU.

What’s the learning curve coming from Zynq-7000?

Engineers familiar with Zynq-7000 will find many similarities—Vivado workflows, AXI interfaces, and PetaLinux tools remain largely consistent. The main learning involves the more complex boot process (PMU, ATF, multiple processor domains), new peripheral features, and 64-bit software considerations. Plan two to four weeks for an experienced Zynq-7000 developer to become productive with UltraScale+ specifics.

How long will AMD support Zynq UltraScale+ devices?

AMD has committed to supporting UltraScale+ FPGAs and adaptive SoCs through 2045, providing 20+ year lifecycles suitable for industrial, medical, and aerospace applications where long-term availability matters. This commitment exceeds typical semiconductor support periods and helps justify design investments in regulated industries.

Making the Platform Decision

The Xilinx Zynq UltraScale+ delivers capabilities unmatched by discrete processor-plus-FPGA solutions. The integration eliminates board-level complexity, reduces power consumption, and enables performance impossible with separate devices.

However, this platform isn’t appropriate for every application. Consider Zynq UltraScale+ when you need:

• 64-bit processing with FPGA acceleration
• Real-time control alongside application processing
• Hardware video codec or GPU capability
• High-speed serial interfaces (USB 3.0, PCIe, SATA)
• Advanced security or functional safety certification
• Long product lifecycle with assured supply

For simpler requirements, the Zynq-7000 family or standalone FPGAs may provide adequate capability at lower cost and complexity. The Kria SOM platform offers an intermediate option—UltraScale+ capability in a production-ready module format that reduces custom hardware development.

Development Workflow Best Practices

Successful Zynq UltraScale+ FPGA projects follow established workflows that manage the inherent complexity of heterogeneous multiprocessing systems.

Hardware-Software Co-Development

Unlike pure software or pure FPGA projects, MPSoC development requires parallel hardware and software work streams. Establish clear interfaces early:

1. Define PS-PL partitioning: Determine which functions run in software versus hardware acceleration
2. Specify AXI interfaces: Document address maps, register definitions, and interrupt assignments
3. Create hardware abstraction: Software teams need APIs that don’t change when hardware evolves
4. Plan verification: Both hardware and software need testable interfaces

Teams commonly underestimate the coordination required between hardware and software development. Weekly interface reviews and shared documentation prevent integration problems.

Recommended Tool Flow

For production Zynq UltraScale+ development:

1. Vivado IP Integrator: Create the hardware platform graphically
2. Export hardware: Generate XSA file for software development
3. Vitis platform creation: Build the software platform from hardware export
4. Application development: Write and debug embedded software
5. PetaLinux integration: Customize Linux for the target hardware
6. System integration: Combine hardware bitstream with software images
7. Production boot image: Create final bootable image for deployment

Maintain version control across all artifacts—Vivado projects, Vitis workspaces, PetaLinux configurations, and custom IP. The interdependencies between these components make reproducible builds essential.

Common Development Pitfalls

After working on numerous Zynq UltraScale+ projects, these issues appear repeatedly:

Inadequate power supply design: The UltraScale+ power sequencing requirements are strict. Violating them causes mysterious failures that waste debugging time.

Underestimating boot complexity: The multi-stage boot process (PMU → FSBL → ATF → U-Boot → Linux) provides many failure points. Instrument each stage for debug output.

Ignoring clock domain crossings: The PS and PL operate on different clock domains. Improper synchronization causes intermittent failures that are difficult to diagnose.

Insufficient PS-PL bandwidth analysis: Many designs underestimate the data movement requirements between processors and accelerators. Profile early and often.

Thermal problems: High-performance devices generate substantial heat. Prototype thermal solutions early, not after the product is designed.

The combination of processing power, programmable logic, and integrated peripherals makes Zynq UltraScale+ particularly compelling for applications at the intersection of software flexibility and hardware performance—exactly where next-generation embedded systems increasingly operate.

Understanding both the capabilities and complexities of this platform enables engineers to make informed decisions about when Xilinx Zynq UltraScale+ represents the right choice versus simpler alternatives. The investment in learning this architecture pays dividends across the entire product family, as skills transfer directly between devices from the smallest CG variants to the largest EV devices.