Zynq-7000 Peripheral Interfaces: I2C, PCIe, USB & More

Working with Zynq-7000 devices means dealing with a rich set of peripheral interfaces. Over the years, I’ve configured everything from simple Zynq I2C sensors to high-speed Zynq USB mass storage systems and even Zynq PCIe root complexes connecting NVMe drives. This guide covers the practical aspects of implementing the most commonly used interfaces on Zynq-7000, with attention to both hardware design and software configuration.

Overview of Zynq-7000 Peripheral Architecture

The Zynq-7000 Processing System (PS) integrates a comprehensive set of peripheral controllers. What makes the architecture interesting is the flexibility in how these peripherals connect to the outside world through either dedicated MIO pins or the Extended MIO (EMIO) interface that routes through programmable logic.

PS Peripheral Controller Summary

Each controller can be enabled independently in Vivado’s PS configuration wizard. The trick is understanding which peripherals share MIO banks and planning your pin assignments accordingly.

Configuring the Zynq I2C Controller

The Zynq I2C interface is probably the most frequently used peripheral for board management tasks. I use it constantly for reading temperature sensors, configuring clock generators, and communicating with EEPROMs. The Zynq-7000 includes two Cadence I2C controllers that support both 100 kHz (standard mode) and 400 kHz (fast mode) operation.

Zynq I2C Hardware Considerations

The I2C signals require external pull-up resistors. The Zynq I2C controller uses open-drain outputs, so the pull-ups are essential for the bus to function properly. For 400 kHz operation, I typically use 2.2kΩ to 4.7kΩ resistors depending on bus capacitance.

Zynq I2C Software Configuration

The I2C controller clock is derived from the CPU_1x clock through programmable dividers. Setting up the proper clock rate requires configuring both DIVA and DIVB registers in the control register.

For 400 kHz operation with a 111 MHz reference clock:

// Clock divider calculation: SCL = CPU_1x / (22 × (DIVA + 1) × (DIVB + 1))

// For 400 kHz: DIVA = 0, DIVB = 12

XIicPs_Config *Config;

XIicPs Iic;

Config = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);

XIicPs_CfgInitialize(&Iic, Config, Config->BaseAddress);

XIicPs_SetSClk(&Iic, 400000);

Common Zynq I2C Issues and Solutions

One gotcha that caught me early on: many datasheets specify 8-bit I2C addresses that include the R/W bit, but the Xilinx driver expects 7-bit addresses. Shift the 8-bit address right by one bit before using it with the driver.

Implementing Zynq USB Interfaces

The Zynq-7000 integrates two USB 2.0 controllers that support host, device, and OTG modes. The Zynq USB interface uses the ULPI protocol to connect to an external PHY chip, which handles the actual USB signaling.

Zynq USB 2.0 Architecture

The USB controller requires an external ULPI PHY like the Microchip USB3320. The PHY handles level shifting, serialization, and the actual USB protocol timing. Most development boards include this PHY already, but for custom designs, pay careful attention to the PHY’s clock requirements and power sequencing.

USB Host Mode Configuration

For USB host mode (connecting flash drives, keyboards, etc.), the Linux driver configuration requires specific kernel options:

Device Drivers —>

    [*] USB support —>

        <*> Support for Host-side USB

        <*> EHCI HCD (USB 2.0) support

        <*> USB Mass Storage support

        <*> ChipIdea Highspeed Dual Role Controller

            [*] ChipIdea host controller

    USB Physical Layer drivers —>

        <*> Generic ULPI Transceiver Driver

The device tree must also include proper Zynq USB configuration:

usb0: usb@e0002000 {

    compatible = “xlnx,zynq-usb-2.20.a”, “chipidea,usb2”;

    clocks = <&clkc 28>;

    dr_mode = “host”;

    interrupt-parent = <&intc>;

    interrupts = <0 21 4>;

    reg = <0xe0002000 0x1000>;

    usb-phy = <&usb_phy0>;

};

Zynq USB 3.0 on Zynq UltraScale+

While the Zynq-7000 only supports USB 2.0, the Zynq UltraScale+ MPSoC adds Zynq USB 3.0 capability through a DWC3 controller. This provides 5 Gbps SuperSpeed operation using the integrated GTR transceivers. The configuration is more complex but follows similar patterns:

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Building a Zynq PCIe Root Complex

Adding PCIe to a Zynq-7000 design requires using the AXI Memory Mapped to PCI Express IP in the programmable logic. This is where Zynq PCIe gets interesting because you’re building a root complex that can host standard PCIe cards like NVMe SSDs, NICs, or custom endpoints.

Zynq PCIe Architecture Options

For a root complex, the AXI-PCIe bridge translates AXI transactions from the PS to PCIe transactions on the external bus. The bridge supports Gen1 (2.5 GT/s) and Gen2 (5 GT/s) speeds with x1, x2, x4, or x8 lane widths depending on your device’s available transceivers.

PCIe Hardware Design Considerations

PCIe requires careful attention to signal integrity. The high-speed serial transceivers (GTX on 7-series) are sensitive to reference clock quality and trace routing.

Linux PCIe Driver Configuration

The AXI PCIe root complex driver is built into the Xilinx Linux kernel. Device tree configuration specifies the memory regions and interrupts:

axi_pcie: axi-pcie@50000000 {

    compatible = “xlnx,axi-pcie-host-1.00.a”;

    reg = <0x50000000 0x10000000>;

    device_type = “pci”;

    interrupts = <0 52 4>;

    ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>;

};

After booting Linux, use lspci to verify endpoint enumeration:

# lspci

00:00.0 PCI bridge: Xilinx Corporation Device 7024

01:00.0 Network controller: Broadcom Inc. BCM4360 802.11ac

Zynq DDR3 Memory Interface

The Zynq DDR3 controller is arguably the most critical interface on the device. It provides the main system memory for both the ARM processors and any PL logic requiring high-bandwidth memory access. Getting Zynq DDR3 wrong means your system doesn’t boot.

DDR3 Controller Capabilities

The controller includes a digital PHY that handles the complex timing relationships between data, strobe, and clock signals. Training and calibration are performed automatically during initialization.

Zynq DDR3 PCB Layout Guidelines

DDR3 routing at 1333 MT/s requires careful attention to signal integrity. The Zynq-7000 uses a fly-by topology for address and command signals with point-to-point connections for data.

Key routing rules I follow:

• Keep DQ to DQS skew within ±5 ps (approximately ±0.8 mm)
• Route address/command signals with matched lengths within ±25 ps
• Maintain reference plane continuity under all DDR traces
• Use 0.1 µF VREF bypass capacitors at memory devices

DDR3 Timing Configuration in Vivado

When configuring the ZYNQ7 Processing System IP, you must provide accurate board trace delays for the memory training algorithms to work correctly:

These values serve as starting points for the DDR training algorithm. The controller performs read/write leveling and eye centering during initialization to compensate for manufacturing variations.

Additional Peripheral Interfaces

SPI Controller

The Zynq includes two SPI controllers that support master and slave modes up to 50 MHz. Common uses include flash memory, ADCs, and display interfaces. I’ve found SPI particularly useful for QSPI boot flash and high-speed DAC/ADC interfaces.

The SPI controller supports all four clock polarity and phase combinations (CPOL/CPHA modes 0-3). For QSPI flash interfaces, use the dedicated Quad-SPI controller which provides 4-bit parallel data transfer for faster boot times.

CAN Bus

For automotive and industrial applications, the dual CAN controllers support CAN 2.0B with speeds up to 1 Mbps. External CAN transceivers (like MCP2551 or TJA1050) are required to interface with the physical bus.

The CAN controllers support both standard (11-bit) and extended (29-bit) identifiers. For applications requiring CAN FD, you’ll need to implement a CAN FD IP in the programmable logic since the PS controllers only support classic CAN.

Gigabit Ethernet (GEM)

The dual Gigabit Ethernet MAC (GEM) controllers provide 10/100/1000 Mbps Ethernet with support for RGMII, GMII, and MII interfaces. Hardware checksum offload and jumbo frame support make these controllers suitable for high-performance networking applications.

For most designs, I use RGMII mode with an external PHY like the Marvell 88E1512 or Microchip KSZ9031. The RGMII interface uses 2.5 MHz, 25 MHz, or 125 MHz clocking depending on the link speed, with DDR data transfer on both clock edges.

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SDIO Controller

The SD/SDIO controllers support SD 2.0, SDHC, and SDXC cards up to 50 MHz clock rate. These interfaces are commonly used for boot media and removable storage.

Essential Resources and Documentation

Official AMD Documentation

Download Links

Xilinx Embedded Software Repository: https://github.com/Xilinx/embeddedsw

Zynq Linux Kernel: https://github.com/Xilinx/linux-xlnx

AMD Adaptive Computing Wiki (Drivers): https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841729/

I2C Driver Examples: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/iicps/examples

USB Driver Examples: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usbps/examples

Frequently Asked Questions

Can I use both Zynq I2C controllers simultaneously?

Yes, both I2C controllers operate independently with their own clock configurations, FIFOs, and interrupt sources. They can run at different speeds and communicate with completely separate sets of slave devices. This is useful for isolating critical devices (like power management) from general-purpose sensors.

Does the Zynq-7000 support Zynq USB 3.0?

No, the Zynq-7000 family only supports USB 2.0 with a maximum speed of 480 Mbps High-Speed. For USB 3.0 support, you need to move to the Zynq UltraScale+ MPSoC family, which includes a DWC3 controller capable of 5 Gbps SuperSpeed operation. Alternatively, you can add USB 3.0 capability to a Zynq-7000 design using a PL-based USB 3.0 controller IP, though this consumes significant logic resources.

What’s the maximum Zynq DDR3 capacity I can use?

The Zynq-7000 DDR controller supports a 1 GB address space with up to 1 GB of DDR3 memory. You can use a single 32-bit wide device or two 16-bit devices in parallel for 32-bit operation. For 16-bit mode, a single 16-bit device up to 512 MB is supported. The limiting factor is typically the address bus width, not the controller itself. For applications needing more memory, consider the Zynq UltraScale+ which supports up to 32 GB of DDR4.

How do I add Zynq PCIe to my design if my device doesn’t have GTX transceivers?

The smaller Zynq devices (7Z007S, 7Z010, 7Z014S) don’t include GTX transceivers, so native PCIe isn’t possible. Your options are: upgrade to a larger Zynq device with GTX (7Z015, 7Z020, 7Z030, 7Z045, 7Z100), use a PCIe-to-AXI bridge chip on your board, or implement a lower-speed parallel bus interface instead. For most applications requiring PCIe, I recommend starting with at least the 7Z020 which includes four GTX transceivers.

Why is my Zynq I2C transaction failing with no ACK?

The most common causes are incorrect slave addressing (using 8-bit address format when the driver expects 7-bit), missing or wrong-value pull-up resistors, voltage level mismatch between the Zynq MIO bank and slave device, or the slave device simply not present or defective. Start debugging by measuring the I2C lines with an oscilloscope to verify you see proper start conditions and address transmission. If the slave isn’t responding at all, verify its power supply and any enable pins before assuming an addressing issue.

Wrapping Up

The Zynq-7000 peripheral interfaces provide everything needed for most embedded applications. The key to success is understanding the relationship between hardware design and software configuration. A well-designed PCB with proper signal integrity for Zynq DDR3 and careful attention to Zynq USB PHY requirements will save countless hours of debugging. Combine that with correct driver configuration for Zynq I2C and other interfaces, and you have a solid foundation for your embedded system.

For complex applications requiring Zynq PCIe or other high-speed interfaces, invest time in simulation and prototyping before committing to a final PCB design. The cost of respinning a board far exceeds the effort of thorough upfront validation.