Xilinx KC705 Evaluation Kit: Unboxing, Setup & First Project

The Xilinx KC705 evaluation kit has been my go-to development platform for prototyping high-speed transceiver designs since it first landed on my bench years ago. Whether you’re evaluating the Kintex-7 architecture for a production design or learning FPGA development, the KC705 delivers serious capability in a well-documented package. This guide walks through everything from initial unboxing to running your first custom project—covering the practical details that official documentation often glosses over.

What is the Xilinx Kintex-7 FPGA KC705 Evaluation Kit?

The EK-K7-KC705-G (the official part number you’ll need for purchasing) is AMD/Xilinx’s flagship development platform for the Kintex-7 FPGA family. Built around the XC7K325T-2FFG900C FPGA, this board provides comprehensive access to the device’s capabilities including high-speed transceivers, DDR3 memory interfaces, PCIe connectivity, and extensive I/O expansion through FMC connectors.

What separates the KC705 from budget-friendly boards is the complete ecosystem: pre-verified reference designs, board design files (schematics, layout, BOM), and ready-to-run demonstrations that actually work out of the box. For teams evaluating Kintex-7 for production hardware, having known-good reference implementations accelerates the learning curve dramatically.

KC705 Board Specifications

KC705 Kit Contents: What’s in the Box

When your EK-K7-KC705-G arrives, verify all components before powering anything up. Missing cables or cards can delay your evaluation by weeks while waiting for replacements.

Complete KC705 Kit Contents

The included Vivado license voucher is particularly valuable—it provides full access to Vivado Design Suite features for the XC7K325T device, saving significant cost compared to purchasing a standalone license.

Xilinx KC705 Board Features and Connectors

Understanding the KC705 board layout before powering up prevents confusion and potential damage from incorrect connections. The board packs considerable functionality into a standard ATX form factor.

Key KC705 Interface Locations

Configuration Mode Settings (SW13)

The 5-position DIP switch SW13 controls how the FPGA loads its bitstream. Getting this wrong is the most common reason for “my board won’t program” issues.

Positions 1 and 2 select which of four bitstreams loads from BPI flash (address bits A25/A24). For initial setup and development, use JTAG mode (SW13 positions 3=ON, 4=OFF, 5=ON).

KC705 Initial Hardware Setup

Before connecting power, complete these preparation steps to ensure safe operation and successful communication with your development PC.

Pre-Power Checklist

Start by verifying jumper settings. The KC705 ships with default settings appropriate for most evaluations, but confirm these critical jumpers:

Connect the USB cable (J26/J27) to your PC before applying power. This provides both JTAG programming access and USB-UART communication for serial console output. Windows will detect a Silicon Labs CP2103 USB-UART bridge—install drivers from Silicon Labs if not automatically recognized.

Power-On Sequence

With SW13 set for JTAG mode and USB connected:

1. Slide SW15 to ON position
2. Observe the power LEDs illuminate (multiple voltage rails)
3. Watch for the DONE LED (DS6) to remain off (no bitstream loaded yet)
4. Verify USB enumeration completes in Device Manager

The board draws approximately 2-3A at 12V with no design loaded, increasing to 4-6A depending on FPGA utilization. Use only the included power supply or an equivalent rated for at least 72W continuous.

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Installing USB Drivers for KC705

The Xilinx KC705 requires two driver sets for full functionality: JTAG programming (handled by Vivado/cable drivers) and USB-UART communication.

USB-UART Driver Installation

The Silicon Labs CP210x driver enables serial console communication:

1. Download CP210x Universal Windows Driver from Silicon Labs
2. Extract and run the installer
3. Connect KC705 via USB
4. Verify COM port assignment in Device Manager (Ports → Silicon Labs CP210x)
5. Note the COM port number for terminal software configuration

JTAG Driver Installation

Vivado installs JTAG drivers automatically, but manual installation may be required:

1. Navigate to C:\Xilinx\Vivado\<version>\data\xicom\cable_drivers\nt64
2. Run install_drivers.cmd as Administrator
3. Reconnect USB cable
4. Verify “Xilinx USB Cable” appears in Device Manager

Running the Built-In Self Test (BIST) on KC705

The KC705 ships with a comprehensive BIST stored in BPI flash. This validates board functionality before investing time in custom development.

BIST Hardware Setup

1. Set SW13 for Master BPI mode (positions 3=OFF, 4=ON, 5=OFF)
2. Set SW13 positions 1 and 2 both to OFF (selects first bitstream)
3. Open terminal software (TeraTerm, PuTTY) at 115200 baud, 8N1
4. Power on the board
5. Watch the FPGA DONE LED illuminate as bitstream loads
6. Observe BIST menu on serial terminal

BIST Test Menu Options

All tests should pass on a functioning board. Failures indicate shipping damage, ESD events, or configuration issues requiring support contact.

Setting Up Vivado for KC705 Development

While the KC705 includes an ISE license voucher historically, modern development uses Vivado Design Suite exclusively. The XC7K325T requires a paid license—the kit’s device-locked voucher covers this.

Vivado Installation Steps

1. Download Vivado from AMD’s website (Vivado ML Standard or Enterprise)
2. Run installer, select “Vivado” product (not Vitis unless needed)
3. Choose device families: ensure “Kintex-7” is selected
4. Complete installation (allow 2-4 hours, requires 50GB+ disk space)
5. Redeem license voucher through AMD licensing portal
6. Install license file via Vivado License Manager

Creating a KC705 Project in Vivado

Launch Vivado and create your first KC705 project:

1. File → Project → New
2. Name project (e.g., “kc705_first_project”)
3. Select RTL Project, check “Do not specify sources”
4. Click Boards tab, search “KC705”
5. Select “Kintex-7 FPGA KC705 Evaluation Platform”
6. Finish wizard

Selecting the board (rather than just the part) pre-populates constraint files and enables board-aware IP configuration in the Block Design flow.

Your First KC705 Project: LED Blinker

The “Hello World” of FPGA development is blinking an LED. This validates your entire toolchain from RTL through bitstream download.

LED Blinker Verilog Code

Create a new source file led_blink.v:

module led_blink (

    input  wire clk_200mhz_p,    // KC705 200MHz differential clock

    input  wire clk_200mhz_n,

    output wire [7:0] gpio_led   // 8 user LEDs

);

    // Differential clock input buffer

    wire clk_200mhz;

    IBUFDS clk_buf (

        .I(clk_200mhz_p),

        .IB(clk_200mhz_n),

        .O(clk_200mhz)

    );

    // 28-bit counter for visible blink rate

    reg [27:0] counter = 0;

    always @(posedge clk_200mhz) begin

        counter <= counter + 1;

    end

    // Drive LEDs from upper counter bits

    assign gpio_led = counter[27:20];

endmodule

KC705 Constraints File

Create led_blink.xdc with pin assignments:

# KC705 200MHz system clock

set_property PACKAGE_PIN AD12 [get_ports clk_200mhz_p]

set_property PACKAGE_PIN AD11 [get_ports clk_200mhz_n]

set_property IOSTANDARD LVDS [get_ports clk_200mhz_p]

set_property IOSTANDARD LVDS [get_ports clk_200mhz_n]

# KC705 GPIO LEDs

set_property PACKAGE_PIN AB8  [get_ports {gpio_led[0]}]

set_property PACKAGE_PIN AA8  [get_ports {gpio_led[1]}]

set_property PACKAGE_PIN AC9  [get_ports {gpio_led[2]}]

set_property PACKAGE_PIN AB9  [get_ports {gpio_led[3]}]

set_property PACKAGE_PIN AE26 [get_ports {gpio_led[4]}]

set_property PACKAGE_PIN G19  [get_ports {gpio_led[5]}]

set_property PACKAGE_PIN E18  [get_ports {gpio_led[6]}]

set_property PACKAGE_PIN F16  [get_ports {gpio_led[7]}]

set_property IOSTANDARD LVCMOS15 [get_ports {gpio_led[*]}]

Building and Programming

1. Add source files to project (Sources → Add Sources)
2. Click “Run Synthesis” in Flow Navigator
3. After synthesis completes, click “Run Implementation”
4. Generate Bitstream when implementation finishes
5. Open Hardware Manager
6. Click “Open Target” → “Auto Connect”
7. Right-click device → “Program Device”
8. Select generated .bit file, click Program

The eight LEDs should now display a binary counting pattern, with LED[0] toggling rapidly and LED[7] changing approximately once per second.

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KC705 Reference Designs and Example Projects

AMD provides extensive reference designs demonstrating KC705 capabilities. These serve as both learning resources and starting points for production development.

Available Reference Designs

Download designs from the KC705 product page Documentation tab or the AMD Adaptive Computing Wiki.

Essential KC705 Documentation and Resources

Official Documentation

Download Links

KC705 Evaluation Kit Frequently Asked Questions

What license is required for KC705 development?

The EK-K7-KC705-G includes a device-locked Vivado license voucher valid for the XC7K325T-2FFG900C. This covers synthesis, implementation, and all design features for this specific device. The license does not expire but only works with the KC705’s FPGA. For multi-device development or different Kintex-7 variants, a separate Vivado license is required.

Can I use ISE instead of Vivado with the KC705?

While the XC7K325T is technically supported in ISE 14.7, AMD recommends Vivado for all 7 Series development. Vivado offers significantly better timing closure, faster compile times, and continued IP support. The kit originally shipped with ISE licenses, but modern kits include Vivado vouchers. Use Vivado unless you have specific legacy requirements.

Why won’t my KC705 program via JTAG?

The most common causes are incorrect SW13 settings (must be in JTAG mode: 3=ON, 4=OFF, 5=ON), missing cable drivers, or USB hub issues. Connect directly to a PC USB port rather than through a hub. Verify the JTAG cable appears in Vivado Hardware Manager. If “No hardware targets” appears, reinstall cable drivers from the Vivado installation directory.

How do I restore the factory BIST after overwriting flash?

Download the KC705 BIST recovery files from the product page. Use Vivado’s Hardware Manager to program the .mcs file to BPI flash. Set SW13 for Master BPI mode and power cycle. The original factory demonstration should boot. Detailed recovery instructions are in UG883.

Is the KC705 still recommended for new designs in 2024?

Yes, the KC705 remains relevant for Kintex-7 development and is supported through AMD’s 2040 device lifecycle commitment. For applications requiring higher performance, consider the KCU105 (Kintex UltraScale) or KCU116 (Kintex UltraScale+). The KC705’s extensive documentation and proven reference designs make it valuable for learning FPGA development regardless of target device.

KC705 Troubleshooting Common Issues

Even with careful setup, you may encounter issues during KC705 development. These troubleshooting tips address the problems I’ve seen most frequently.

Power-Related Problems

If the power LED doesn’t illuminate or the board behaves erratically, verify the 12V supply delivers adequate current. Some generic laptop adapters share the same barrel connector but can’t source the 4-6A the KC705 demands under load. The included adapter is rated appropriately—use it or an equivalent 72W+ supply. Check that no FMC cards are installed that might have shorts or excessive current draw.

Programming Failures

When Vivado shows “No hardware targets found,” the issue is usually driver-related. Reinstall cable drivers, try a different USB port (avoid USB 3.0 ports initially—some have compatibility issues), and ensure no other Xilinx tools are running simultaneously. If programming succeeds but the design doesn’t run, verify your constraints file matches the actual KC705 pinout—pin assignments from other boards won’t work.

DDR3 Memory Issues

The MIG (Memory Interface Generator) IP requires specific timing constraints and board parameters. When creating MIG instances for KC705, select the board preset rather than manually entering parameters. The preset includes the correct SODIMM configuration, timing, and termination values. Custom configurations require careful attention to UG586 guidelines.

Expanding KC705 Capability with FMC Cards

The KC705’s FMC connectors enable significant capability expansion through daughter cards. The VITA-57 standard defines pinouts for both high-pin-count (HPC) and low-pin-count (LPC) configurations.

Popular FMC Expansion Cards

The HPC connector (J22) provides 4 GTX transceiver lanes plus extensive LVDS I/O, while the LPC connector (J30) offers 1 GTX lane and reduced I/O count. Note that the KC705’s HPC connector is partially populated—not all HPC-spec pins are present.

Conclusion

The Xilinx KC705 evaluation kit provides a comprehensive platform for Kintex-7 FPGA development, from initial learning through production prototyping. The combination of high-speed transceivers, DDR3 memory, and extensive connectivity options in a well-documented package accelerates development timelines significantly.

Start with the BIST to verify board functionality, then work through the LED blinker project to validate your toolchain. From there, explore the reference designs matching your application—whether that’s PCIe DMA, 10G Ethernet, or embedded MicroBlaze systems. The investment in learning the KC705 platform pays dividends across the entire Kintex-7 and broader 7 Series FPGA family.

For teams evaluating Kintex-7 for production, the KC705 board files (schematics, layout, BOM) provide a proven starting point for custom carrier board development. The XC7K325T’s balance of logic density, DSP capability, and transceiver performance addresses demanding applications from wireless infrastructure to video processing to medical imaging.