XC9572XL CPLD: Pinout, Programming & Getting Started Guide

If you’ve ever spent hours hunting through component catalogs trying to find the perfect combination of logic chips for your project, you’re not alone. The Xilinx XC9572XL CPLD offers a smarter solution: program your own custom logic chip with exactly the functionality you need.

I’ve been working with these devices in various designs over the years, from replacing obsolete glue logic to building custom interfaces for legacy systems. The XC9572XL strikes a sweet spot between capability and simplicity that makes it particularly appealing for embedded projects, prototype development, and production designs where you need deterministic timing without the complexity of an FPGA.

This guide covers everything you need to get started with the XC9572XL, from understanding its architecture to programming your first design.

What is the Xilinx XC9572XL CPLD?

The XC9572XL belongs to Xilinx’s XC9500XL family of Complex Programmable Logic Devices. Unlike simple PLDs or massive FPGAs, CPLDs occupy a middle ground, providing enough logic resources for moderately complex designs while maintaining the non-volatile, instant-on characteristics that many applications require.

At its core, the XC9572XL provides 72 macrocells organized into four function blocks. Each macrocell can be configured as either a combinatorial logic element or a registered (flip-flop) element depending on your design requirements. The device offers approximately 1,600 usable gates, which is sufficient for many glue logic applications, state machines, bus interfaces, and control functions.

What makes the XC9572XL particularly practical is its operating voltage configuration. The core runs on 3.3V, but all I/O pins are 5V tolerant, meaning you can interface directly with older TTL logic without level shifters. Output levels can be set to either 3.3V or 2.5V depending on your VCCIO supply.

XC9572XL Key Features at a Glance

XC9572XL Architecture Overview

Understanding the internal architecture helps you write more efficient designs and troubleshoot issues when things don’t work as expected.

Function Blocks and the FastCONNECT II Switch Matrix

The XC9572XL contains four identical function blocks, each with 18 macrocells. These function blocks connect through the FastCONNECT II switch matrix, which provides a programmable interconnect allowing any signal to route to any function block input.

Each function block receives 54 inputs from the switch matrix, giving you substantial flexibility in how signals route through the device. The outputs from each function block can drive I/O pins directly or feed back into the switch matrix for use by other function blocks.

Macrocell Structure

Each macrocell within the XC9572XL can implement either combinatorial logic or sequential logic:

• Combinatorial mode uses the product-term array to create sum-of-products logic expressions
• Sequential mode adds a configurable flip-flop with individual clock, enable, and preset/reset controls

The device supports up to 90 product terms per macrocell through the product-term allocator. This allocator can borrow unused product terms from adjacent macrocells when your design requires more complex logic expressions.

Global Signals

The XC9572XL provides three types of global signals that distribute across the entire device with minimal skew:

These global signals connect through optimized routing paths. If your design uses clocks, connecting them to GCK pins ensures the best possible timing performance. However, if you don’t explicitly enable these features in your design, the pins function as normal I/O.

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XC9572XL Pinout by Package

One of the trickiest aspects of working with the XC9572XL is selecting the right package and correctly mapping your signals. The device comes in five package options with varying I/O counts.

Package Options Comparison

VQ44 Package Pinout

The 44-pin VQFP package is the most common choice for hobbyist and prototype work. Here’s the critical pin mapping:

PC44 vs VQ44: A Common Pitfall

A word of caution from experience: the PC44 (PLCC) and VQ44 (VQFP) packages have completely different pinouts despite both having 44 pins. I’ve seen more than one designer waste hours debugging a board only to discover they selected the wrong package in their constraint file.

Always double-check that your UCF file specifies the correct package. For the VQ44, your ISE project should show “VQ44” in the device properties, not “PC44”.

Power Supply Requirements

Getting the power supply right is essential for reliable operation. The XC9572XL requires two supply rails:

VCCINT (Core Supply)

• Voltage Range: 3.0V to 3.6V (nominal 3.3V)
• Powers internal logic and JTAG interface
• Multiple pins on larger packages for improved power distribution

VCCIO (I/O Supply)

• 3.3V operation: 3.0V to 3.6V
• 2.5V operation: 2.3V to 2.7V
• Sets output voltage levels
• Must not exceed VCCINT

Decoupling Capacitors

Proper decoupling prevents glitches and ensures reliable operation:

Place decoupling capacitors as close to the power pins as possible. For the VQ44 package, a single 100nF capacitor per supply rail is the minimum; adding a bulk 10µF capacitor near the power connector improves transient response.

Programming the XC9572XL: Step-by-Step Guide

Programming the XC9572XL follows a workflow that might feel different if you’re coming from a microcontroller background. Instead of writing sequential code, you describe the hardware behavior using a Hardware Description Language (HDL) or schematic capture.

Required Tools and Software

Xilinx ISE WebPack: This is the development environment for XC9500XL CPLDs. Download version 14.7 from Xilinx/AMD, which is the final version supporting these devices. The download is substantial (around 4.6GB) and the installation requires approximately 11GB of disk space.

JTAG Programmer: Several options exist:

Development Workflow

The basic workflow for any XC9572XL project follows these steps:

1. Create the design using Verilog, VHDL, or schematic entry
2. Synthesize the design to generate a netlist
3. Implement the design (fit it to the CPLD architecture)
4. Generate the programming file (.jed or .xsvf)
5. Program the device through JTAG

Creating a Project in ISE WebPack

When creating a new project in ISE, select these device options:

• Device Family: XC9500XL CPLDs
• Device: XC9572XL
• Package: VQ44 (or your actual package)
• Speed: -10 (or your speed grade)

Writing Your First Design: LED Blinker

Here’s a simple Verilog design that toggles an LED, useful for verifying your toolchain and hardware setup:

module led_blink(

    input clk,

    output reg led

);

reg [23:0] counter;

always @(posedge clk) begin

    counter <= counter + 1;

    if (counter == 24’d0)

        led <= ~led;

end

endmodule

Pin Constraints (UCF File)

After writing your HDL, you need to tell the tools which physical pins to use. Create a User Constraints File (.ucf):

NET “clk” LOC = “P43”;  # GCK1 pin

NET “led” LOC = “P39”;  # General I/O pin

Use GCK pins for clock inputs to get the best timing performance. The LOC constraint specifies the physical pin number.

Generating and Downloading the Programming File

After synthesis and implementation complete successfully:

1. Expand “Generate Programming File” in the process panel
2. Right-click “Generate Programming File” and select “Run”
3. This creates a .jed file containing the fuse map

To program with an official Xilinx cable:

1. Double-click “Configure Target Device”
2. iMPACT will launch and detect your JTAG chain
3. Assign the .jed file to the XC9572XL device
4. Right-click and select “Program”

Alternative Programming Methods

If you’re using a third-party programmer like the Bus Pirate or xc3sprog, you’ll need to convert the .jed file to XSVF format:

1. In iMPACT, create a new project
2. Add your .jed file to the device
3. Right-click and select “Create new SVF/XSVF File”
4. Use your programmer’s utility to play the XSVF file

Common Applications for the XC9572XL

The XC9572XL excels in applications requiring fast, deterministic logic that doesn’t need the resources of an FPGA.

Glue Logic Replacement

Replace multiple 7400-series or 4000-series logic ICs with a single CPLD. This approach reduces board space, simplifies routing, and allows design changes without PCB modifications.

Bus Interface and Protocol Conversion

The XC9572XL handles tasks like:

• Address decoding for memory-mapped peripherals
• SPI to parallel conversion
• Custom serial protocol implementation
• Level shifting between voltage domains

State Machine Implementation

Finite state machines for control applications fit well in the XC9572XL. With 72 flip-flops available, you can implement moderately complex state machines with multiple outputs.

Legacy System Interfaces

The 5V tolerant inputs make the XC9572XL ideal for interfacing modern microcontrollers with older equipment. I’ve used them for connecting ARM processors to vintage computer buses.

Clock Division and Timing

Using the internal flip-flops, you can create clock dividers and timing generators. However, note that the XC9572XL doesn’t include a PLL or DLL, so clock multiplication requires an external oscillator.

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XC9572XL vs Other CPLDs: Making the Right Choice

The XC9572XL isn’t always the best option. Here’s how it compares to alternatives:

XC9572XL vs XC9572 (5V Version)

The XL version is generally preferred unless you specifically need 5V output levels.

XC9572XL vs CoolRunner-II

The CoolRunner-II (XC2C series) offers:

• Lower power consumption (good for battery applications)
• Multiple I/O voltage banks
• Built-in clock divider
• Internal pull-up resistors

However, it requires separate 1.8V core supply, adding board complexity.

When to Use an FPGA Instead

Consider an FPGA if you need:

• More than 1,600 gates
• Block RAM or distributed memory
• PLLs for clock manipulation
• DSP blocks
• High-speed serial interfaces

Troubleshooting Common XC9572XL Issues

Working with CPLDs involves some common pitfalls that are worth knowing about upfront.

Programming Failures

If programming fails, check these items:

1. VCCIO must be connected, even during programming (this catches many people)
2. Verify your JTAG connections (TCK, TDI, TDO, TMS, GND)
3. Power cycle the board after programming; the CPLD doesn’t automatically load new configuration
4. Ensure you selected the correct package in your project settings

Design Doesn’t Fit

If your design exceeds the device resources:

• Check the synthesis report for macrocell and product term usage
• Enable low-power mode on non-critical paths (reduces product term count)
• Consider restructuring combinatorial logic to share product terms
• Use registered outputs where timing allows

Timing Issues

The XC9572XL provides predictable timing, but issues can arise:

• Connect clocks to GCK pins for best performance
• Use GSR for synchronous reset instead of asynchronous
• Review the timing report for paths that exceed your requirements

Useful Resources for XC9572XL Development

Datasheets and Documentation

Development Board Options

Software Downloads

• Xilinx ISE WebPack 14.7: Available from AMD’s website (legacy products section)
• xc3sprog: Open-source programmer supporting Raspberry Pi and FT2232
• UrJTAG: Universal JTAG tool for SVF playback

FAQs About the XC9572XL CPLD

Can the XC9572XL interface with 5V logic?

Yes, all I/O pins are 5V tolerant on inputs. The device accepts 5V, 3.3V, and 2.5V input levels. However, outputs are limited to VCCIO voltage (3.3V or 2.5V depending on your configuration). For driving 5V logic, the 3.3V output level generally meets TTL input thresholds (VIH minimum of 2.0V).

How many times can I reprogram the XC9572XL?

The device is rated for at least 10,000 program/erase cycles with 20-year data retention. In practical terms, you can reprogram it thousands of times during development without concern for wear-out.

Does the XC9572XL retain its configuration when powered off?

Yes, the XC9572XL uses non-volatile Flash technology. Unlike SRAM-based FPGAs, it retains its configuration without external memory and powers up immediately with your design active. This makes it ideal for applications requiring instant-on behavior.

What’s the difference between XC9572XL speed grades (-5, -7, -10)?

The speed grade indicates the fastest pin-to-pin propagation delay: -5 means 5ns, -7 means 7.5ns, and -10 means 10ns. The -5 grade also supports higher system frequencies (178 MHz vs 100 MHz for -10). Choose based on your timing requirements and budget.

Can I read back the configuration from an XC9572XL?

By default, yes. However, the device supports security bits that can be programmed to prevent readback, protecting your intellectual property. Once security is enabled, it can only be cleared by erasing the entire device.

Final Thoughts

The XC9572XL remains a practical choice for digital designers who need programmable logic without FPGA complexity. Its 5V tolerant inputs, instant-on operation, and straightforward toolchain make it particularly useful for interfacing, glue logic, and control applications.

While newer devices offer more features, the XC9572XL’s simplicity is often an advantage. You can have a working design programmed into hardware within an hour of starting, which is hard to beat for quick prototyping or learning programmable logic fundamentals.

Start with a development board, work through the LED blinker example, and gradually tackle more complex projects. The concepts you learn apply directly to FPGAs when you’re ready to scale up to larger designs.