XC6SLX9 FPGA Tutorial: Pinout, Programming & Projects

The XC6SLX9 has become one of the most popular FPGAs for learning digital design and building embedded systems. As a member of the Xilinx Spartan 6 family, this device hits a sweet spot between capability and accessibility that makes it ideal for students, hobbyists, and professionals working on cost-sensitive projects. I’ve used this chip across numerous prototypes over the years, and this tutorial will share everything you need to get started—from understanding the pinout to programming your first project.

Whether you’re picking up your first Xilinx Spartan 6 XC6SLX9 FPGA development board or migrating from microcontrollers to programmable logic, this guide provides the practical knowledge you need.

What is the XC6SLX9 FPGA?

The XC6SLX9 is a member of the Xilinx Spartan-6 LX family, manufactured on a 45nm process. It sits in the lower-middle of the Spartan-6 lineup, offering enough resources for real projects while remaining affordable for educational purposes.

Unlike a microcontroller that executes sequential instructions, the Xilinx XC6SLX9 implements actual digital circuits in programmable logic. This means you can create custom hardware—parallel processing, precise timing control, and dedicated peripherals—all reconfigurable with a simple bitstream upload.

XC6SLX9 Key Specifications

Specification	Value
Logic Cells	9,152
CLB Slices	1,430
Slice Registers (Flip-Flops)	11,440
Slice LUTs	5,720
Block RAM	576 Kb (32 × 18 Kb blocks)
DSP48A1 Slices	16
CMTs (Clock Management Tiles)	2
Maximum User I/O	200
Global Clock Buffers	16
Process Technology	45nm
Core Voltage	1.0V (-1L) or 1.2V (-2, -3)

The 9,152 logic cells provide enough capacity for implementing UART controllers, VGA drivers, SPI/I2C masters, simple processors, and various signal processing blocks. The 16 DSP slices handle multiplication and accumulation operations efficiently for filter implementations.

Xilinx Spartan 6 SLX9 Package Options

The Xilinx Spartan 6 SLX9 comes in several package variants. Your choice affects PCB layout complexity, available I/O count, and whether you can hand-solder the device.

Package	Pins	Max User I/O	Body Size	Ball Pitch
TQG144	144	102	20 × 20 mm	TQFP 0.5mm
CSG225	225	160	13 × 13 mm	BGA 0.8mm
CSG324	324	200	15 × 15 mm	BGA 0.8mm
FTG256	256	186	17 × 17 mm	BGA 1.0mm

For hobbyists and prototyping, the TQG144 package is the go-to choice. It’s a standard TQFP with 0.5mm pin pitch—challenging but achievable with a fine-tip soldering iron and flux. The BGA packages require reflow soldering equipment.

XC6SLX9 Pinout Overview

Understanding the XC6SLX9 pinout is essential for both custom PCB design and working with development boards. The 144-pin TQFP variant (TQG144) organizes pins into distinct categories.

Pin Categories

Pin Type	Count (TQG144)	Description
User I/O	102	General-purpose programmable I/O
Power (VCCINT)	8	1.2V core supply
Power (VCCAUX)	8	2.5V or 3.3V auxiliary supply
Power (VCCO)	12	I/O bank supply (1.2V–3.3V)
Ground (GND)	12	Ground connections
Configuration	6	JTAG, PROGRAM_B, DONE, etc.
Clock	4	Dedicated clock inputs

I/O Bank Organization

The XC6SLX9 TQG144 package includes two I/O banks, each with independent VCCO power:

Bank	User I/O Count	VCCO Options	Notes
Bank 0	34	1.2V–3.3V	Contains configuration pins
Bank 2	68	1.2V–3.3V	Main user I/O bank

Each bank supports different I/O standards based on the VCCO voltage:

VCCO Voltage	Supported Standards
3.3V	LVCMOS33, LVTTL
2.5V	LVCMOS25, SSTL25
1.8V	LVCMOS18, SSTL18
1.5V	LVCMOS15, SSTL15
1.2V	LVCMOS12

Essential Configuration Pins

These pins control FPGA configuration and must be properly connected:

Pin Name	Pin Number (TQG144)	Function
PROGRAM_B	P38	Active-low reconfiguration trigger
DONE	P53	Configuration complete indicator
INIT_B	P40	Initialization status
TCK	P109	JTAG clock input
TDI	P110	JTAG data input
TDO	P106	JTAG data output
TMS	P107	JTAG mode select
CCLK	P70	Configuration clock

For SPI flash configuration (common on development boards), additional pins come into play:

Pin Name	Pin Number	Function
VS0/MOSI	P64	SPI data out (to flash MOSI)
VS1/DIN	P65	SPI data in (from flash MISO)
VS2/CSO_B	P38	SPI chip select

Read more Xilinx FPGA Series:

Xilinx Spartan 6 XC6SLX9 FPGA Development Board Options

Rather than designing a custom PCB, most people start with a Xilinx Spartan 6 XC6SLX9 FPGA development board. Several affordable options exist:

Board	Price Range	Key Features
Mimas (Numato)	~$40	USB config, 70 I/O, SPI flash
ALINX AX309	~$50	SDRAM, VGA, 7-segment, UART
easyFPGA-Spartan-6	~$35	SDRAM, VGA, PS/2, ADC
EDGE Spartan 6	~$60	WiFi, Bluetooth, VGA, LCD
XC6SLX9 Mini Board	~$25	72 I/O, USB-UART, compact
Mojo V3 (Embedded Micro)	~$80	Arduino shield compatible

What to Look for in a Development Board

When selecting a Xilinx Spartan 6 XC6SLX9 FPGA development board, consider:

Programming interface: USB-based programming (via onboard controller) is most convenient. JTAG headers allow use with Xilinx Platform Cable USB if needed.

Configuration storage: Onboard SPI flash enables boot-from-power-on functionality. Without it, you’ll need to reprogram after every power cycle.

Clock source: A 50 MHz oscillator is standard. Some boards include multiple clock options.

Peripheral interfaces: VGA output, UART, buttons, LEDs, and expansion headers extend learning possibilities.

Power supply: USB-powered boards simplify setup. Some designs require external 5V for peripherals.

Programming the XC6SLX9: ISE Design Suite Setup

The XC6SLX9 requires Xilinx ISE Design Suite for development. Unlike newer Xilinx devices that use Vivado, Spartan-6 is only supported in ISE.

Installing ISE 14.7

ISE 14.7 is the final release and remains available for free download:

Component	Details
Software	ISE Design Suite 14.7
License	WebPACK (free)
Download Size	~6.5 GB
OS Support	Windows 7 (native), Windows 10/11 (VM)

ISE doesn’t install cleanly on Windows 10/11. The recommended approach is using the pre-configured virtual machine image AMD provides, which runs under VirtualBox.

Creating Your First Project

Here’s the workflow for implementing a design on the Xilinx XC6SLX9:

Step 1: Create New Project

• Open ISE Project Navigator
• File → New Project
• Set project name and location
• Select device: Family = Spartan6, Device = XC6SLX9, Package = TQG144 (or your board’s package), Speed = -2

Step 2: Add HDL Source Files

• Create new source (VHDL or Verilog)
• Write your design

Step 3: Create UCF Constraints File

• Add new source → Implementation Constraints File
• Map logical signals to physical pins

Step 4: Synthesize and Implement

• Double-click “Synthesize – XST”
• Double-click “Implement Design”
• Double-click “Generate Programming File”

Step 5: Program the FPGA

• Use iMPACT (JTAG) or board-specific tool (USB)
• Select the generated .bit file

UCF File Format

The User Constraints File (UCF) maps your HDL ports to physical XC6SLX9 pins:

# Clock input (50 MHz oscillator)

NET “clk” LOC = P126;

NET “clk” IOSTANDARD = LVCMOS33;

# Push buttons

NET “btn<0>” LOC = P124;

NET “btn<1>” LOC = P123;

NET “btn<0>” IOSTANDARD = LVCMOS33;

NET “btn<1>” IOSTANDARD = LVCMOS33;

# LEDs

NET “led<0>” LOC = P44;

NET “led<1>” LOC = P43;

NET “led<0>” IOSTANDARD = LVCMOS33;

NET “led<1>” IOSTANDARD = LVCMOS33;

Pin numbers vary between development boards—always reference your board’s schematic or provided UCF template.

XC6SLX9 Beginner Projects

Learning FPGA development is best done through hands-on projects. Here are progressive examples suitable for the XC6SLX9:

Project 1: LED Blinker

The “Hello World” of FPGA—blink an LED using a clock divider:

module led_blink(

    input clk,        // 50 MHz clock

    output reg led    // LED output

);

reg [25:0] counter;

always @(posedge clk) begin

    counter <= counter + 1;

    if (counter == 0)

        led <= ~led;

end

endmodule

This creates approximately 1.3-second blink period from a 50 MHz clock.

Resource usage: ~30 LUTs, ~27 registers

Project 2: Button Debouncer with LED Control

Physical buttons bounce—the contact makes and breaks multiple times during a press. This project implements proper debouncing:

module button_led(

    input clk,

    input btn,

    output reg led

);

reg [19:0] debounce_counter;

reg btn_stable;

reg btn_prev;

always @(posedge clk) begin

    if (btn != btn_stable) begin

        debounce_counter <= debounce_counter + 1;

        if (debounce_counter == 20’hFFFFF) begin

            btn_stable <= btn;

            debounce_counter <= 0;

        end

    end else begin

        debounce_counter <= 0;

    end

    btn_prev <= btn_stable;

    if (btn_stable && !btn_prev)  // Rising edge

        led <= ~led;

end

endmodule

Resource usage: ~50 LUTs, ~45 registers

Project 3: UART Transmitter

Serial communication is fundamental. This implements a basic 115200 baud transmitter:

module uart_tx(

    input clk,           // 50 MHz

    input [7:0] data,

    input send,

    output reg tx,

    output reg busy

);

parameter CLKS_PER_BIT = 434;  // 50MHz / 115200

reg [9:0] shift_reg;

reg [8:0] clk_count;

reg [3:0] bit_index;

always @(posedge clk) begin

    if (!busy && send) begin

        shift_reg <= {1’b1, data, 1’b0};  // Stop, data, start

        busy <= 1;

        bit_index <= 0;

        clk_count <= 0;

    end else if (busy) begin

        if (clk_count < CLKS_PER_BIT – 1) begin

            clk_count <= clk_count + 1;

        end else begin

            clk_count <= 0;

            tx <= shift_reg[0];

            shift_reg <= {1’b1, shift_reg[9:1]};

            if (bit_index < 9)

                bit_index <= bit_index + 1;

            else

                busy <= 0;

        end

    end

end

endmodule

Resource usage: ~80 LUTs, ~35 registers

Read more Xilinx Products:

Project 4: VGA Color Bars

Many XC6SLX9 development boards include VGA output. This generates 640×480 color bars:

module vga_colorbar(

    input clk,           // 50 MHz, divided to 25 MHz pixel clock

    output reg hsync,

    output reg vsync,

    output reg [3:0] red,

    output reg [3:0] green,

    output reg [3:0] blue

);

// VGA 640×480 @ 60Hz timing

parameter H_VISIBLE = 640;

parameter H_FRONT = 16;

parameter H_SYNC = 96;

parameter H_BACK = 48;

parameter V_VISIBLE = 480;

parameter V_FRONT = 10;

parameter V_SYNC = 2;

parameter V_BACK = 33;

reg [9:0] h_count;

reg [9:0] v_count;

reg pclk;

// Generate 25 MHz pixel clock from 50 MHz

always @(posedge clk)

    pclk <= ~pclk;

always @(posedge pclk) begin

    // Horizontal counter

    if (h_count < H_VISIBLE + H_FRONT + H_SYNC + H_BACK – 1)

        h_count <= h_count + 1;

    else begin

        h_count <= 0;

        // Vertical counter

        if (v_count < V_VISIBLE + V_FRONT + V_SYNC + V_BACK – 1)

            v_count <= v_count + 1;

        else

            v_count <= 0;

    end

    // Sync signals (active low)

    hsync <= ~((h_count >= H_VISIBLE + H_FRONT) &&

               (h_count < H_VISIBLE + H_FRONT + H_SYNC));

    vsync <= ~((v_count >= V_VISIBLE + V_FRONT) &&

               (v_count < V_VISIBLE + V_FRONT + V_SYNC));

    // Color bars based on horizontal position

    if (h_count < H_VISIBLE && v_count < V_VISIBLE) begin

        case (h_count[9:7])  // 8 vertical bars

            3’d0: begin red <= 4’hF; green <= 4’hF; blue <= 4’hF; end  // White

            3’d1: begin red <= 4’hF; green <= 4’hF; blue <= 4’h0; end  // Yellow

            3’d2: begin red <= 4’h0; green <= 4’hF; blue <= 4’hF; end  // Cyan

            3’d3: begin red <= 4’h0; green <= 4’hF; blue <= 4’h0; end  // Green

            3’d4: begin red <= 4’hF; green <= 4’h0; blue <= 4’hF; end  // Magenta

            3’d5: begin red <= 4’hF; green <= 4’h0; blue <= 4’h0; end  // Red

            3’d6: begin red <= 4’h0; green <= 4’h0; blue <= 4’hF; end  // Blue

            3’d7: begin red <= 4’h0; green <= 4’h0; blue <= 4’h0; end  // Black

        endcase

    end else begin

        red <= 4’h0; green <= 4’h0; blue <= 4’h0;

    end

end

endmodule

Resource usage: ~120 LUTs, ~45 registers

Project 5: Seven-Segment Display Multiplexer

Drive multiple 7-segment digits with time-multiplexing:

Resource usage: ~90 LUTs, ~50 registers

These projects form a solid foundation. From here, you can explore SPI flash interfaces, I2C sensors, PWM motor control, and even soft processor implementations like PicoBlaze.

Advanced XC6SLX9 Applications

Once comfortable with basics, the Xilinx Spartan 6 SLX9 supports more sophisticated projects:

Application	Typical Resource Usage	Notes
PicoBlaze Processor	~100 LUTs	Simple 8-bit soft processor
I2C Master	~150 LUTs	Interface to sensors, EEPROMs
SPI Master	~80 LUTs	Flash, ADC, DAC interfaces
PWM Controller	~50 LUTs per channel	Motor control, LED dimming
PS/2 Keyboard	~100 LUTs	Keyboard/mouse interface
SD Card Controller	~400 LUTs	FAT filesystem access
Audio DAC (PWM)	~60 LUTs	Simple audio output
Frequency Counter	~200 LUTs	Measurement applications

The 576 Kb of Block RAM enables frame buffers, lookup tables, and data buffering. The 16 DSP slices efficiently implement FIR filters, audio processing, and mathematical functions.

Useful Resources and Downloads

Official Documentation

Document	Content
DS160	Spartan-6 Family Overview
DS162	DC and AC Switching Characteristics
UG380	Configuration User Guide
UG381	SelectIO Resources
UG382	Clocking Resources
UG383	Block RAM Resources
UG384	Configurable Logic Block
UG385	Packaging and Pinouts
UG388	Memory Controller User Guide
UG389	DSP48A1 Slice User Guide

Software Downloads

• ISE Design Suite 14.7 WebPACK — AMD/Xilinx Archive Downloads
• ISE Virtual Machine — Pre-configured VM for Windows 10/11
• Platform Cable USB II Drivers — For JTAG programming

Community Resources

• GitHub: ALINX-AX309 Projects — Lab examples for XC6SLX9 boards
• GitHub: spartan-6-xc6slx9-rz-easyfpga-x1 — Pin definitions and examples
• AllAboutFPGA.com — Tutorials and EDGE board resources
• Numato Lab Help Center — Mimas board documentation
• FPGA4Fun.com — General FPGA tutorials

Development Board Resources

Most board manufacturers provide:

• Schematic PDFs
• UCF constraint files
• Example projects
• User manuals

Download these before starting development—the UCF file alone saves hours of pin mapping work.

Frequently Asked Questions

Can I program the XC6SLX9 with Vivado?

No. The XC6SLX9 and all Spartan-6 devices require ISE Design Suite. Vivado only supports 7 Series and newer FPGAs. ISE 14.7 WebPACK is free and includes all necessary tools for Spartan-6 development.

What’s the difference between XC6SLX9-2TQG144C and XC6SLX9-2TQG144I?

The suffix indicates temperature grade: “C” is commercial (0°C to +85°C) and “I” is industrial (-40°C to +100°C). The “-2” indicates speed grade. For most hobbyist and development work, commercial grade is sufficient and typically lower cost.

How do I store my design permanently on the XC6SLX9?

The XC6SLX9 uses SRAM-based configuration—it loses programming when powered off. To make designs persistent, program an external SPI flash (like M25P16 or W25Q64). Most development boards include this flash and boot automatically from it. In ISE, generate an MCS file using iMPACT’s PROM File Formatter, then program the flash via JTAG.

Is the XC6SLX9 suitable for learning FPGA development?

Yes, the Xilinx XC6SLX9 is an excellent learning device. Its 9,152 logic cells handle meaningful projects without being overwhelming. The availability of inexpensive development boards (under $50) and free tools makes it accessible. The main drawback is ISE’s age—newer devices use Vivado, which offers a better development experience.

What programming cable do I need for the XC6SLX9?

It depends on your development board. Many modern boards include USB-based configuration and don’t require an external programmer. For boards with only JTAG headers, you’ll need a Xilinx Platform Cable USB or compatible clone. Some boards work with generic FTDI-based JTAG adapters using third-party tools like xc3sprog.

Conclusion

The XC6SLX9 remains a capable and affordable entry point into FPGA development. While it’s built on older technology and requires legacy tools, the fundamental concepts you learn apply directly to newer devices. The wealth of available development boards, documentation, and community projects makes it straightforward to get started.

Start with the LED blinker, progress through UART and VGA projects, and you’ll develop an intuition for hardware description that transfers to any FPGA family. The investment in learning pays dividends when you need custom digital logic that no microcontroller can match.

For those ready to move beyond the Xilinx Spartan 6 SLX9, the natural progression is to Spartan-7 or Artix-7 devices, which offer improved performance, lower power consumption, and the modern Vivado toolchain—but the design principles remain the same.