PCB Laminate Stack-Up Design: Selecting Materials for Each Layer

A complete PCB stack-up laminate material selection guide — covering core vs prepreg, glass style selection, layer-by-layer material assignment, hybrid stackup design, symmetry rules, and reference tables for 4, 6, and 8-layer builds.

The stackup is the first engineering decision on any multilayer PCB — and it’s the one that locks in signal integrity headroom, thermal performance, and manufacturing cost before a single trace is routed. Most of the design mistakes that get discovered on the bench trace back to stackup decisions that were made quickly, defaulted to whatever the fab shop suggested, or copied from a previous project without examining whether the material selections actually fit the new application. This guide on PCB stack-up laminate material selection covers the complete layer-by-layer decision process: what goes where, which material type belongs in each position, how glass style and resin content affect your impedance calculations, and what a hybrid stackup looks like when your design mixes RF and digital functionality.

Why PCB Stack-Up Laminate Material Selection Is an Engineering Decision, Not a Procurement Decision

Engineers often treat the stackup as something the fabricator fills in after the Gerbers are submitted. Experienced designers know it works the other way around — the stackup defines the dielectric thicknesses that determine your 50Ω trace widths, the material choices that determine your insertion loss budget, and the construction symmetry that determines whether your board warps during lamination. Changing the stackup after layout has started means re-doing impedance-matched traces. Changing it after prototypes are built means a respin. Getting it right before layout starts costs a half-day of engineering work.

The starting point for any PCB stack-up laminate material selection exercise is three questions: What is the highest frequency or data rate carried by any signal on this board? What is the operating temperature environment? And what does the total board thickness need to be? Those three answers drive most of what follows.

Understanding the Two Physical Building Blocks: Core and Prepreg

Every multilayer PCB is built from two types of dielectric material. Understanding the difference between them is foundational to making sensible stackup material decisions.

Core is fully cured laminate — fiberglass cloth impregnated with epoxy resin, pressed, and cured to a rigid state, with copper foil laminated to one or both sides. Core provides mechanical rigidity, hosts the inner-layer copper traces, and has stable, predictable dielectric properties because it is already fully cured before it enters your stackup. Common core thicknesses range from 0.1 mm to 1.6 mm. The Dk of a core layer is reliable and consistent with the manufacturer’s datasheet.

Prepreg (pre-impregnated) is fiberglass cloth impregnated with partially cured (B-stage) epoxy resin — no copper, semi-flexible, and adhesive at room temperature. During lamination, heat and pressure cause the resin to flow, bond to adjacent core and copper layers, and fully cure. Prepreg serves as the bonding layer between cores in a multilayer stackup, as well as the dielectric layer between each core’s outer copper face and the next element in the build. The Dk of prepreg after lamination differs slightly from the core Dk because resin content, flow, and glass style all vary — and those variations directly affect your trace impedance calculations.

The practical difference: for any layer where you need the most predictable, tightest-tolerance Dk — typically the layers adjacent to critical controlled-impedance signals — prefer core-based dielectric spacing over prepreg-only spacing. For layers where thickness flexibility matters most (non-critical power/signal separation), prepreg thickness can be tuned by selecting glass style and ply count.

Glass Fiber Weave Styles: The Variable Nobody Explains Until It Matters

The fiberglass cloth inside your laminate is woven in standardised styles identified by numbers: 106, 1080, 2116, and 7628 are the most common. These aren’t arbitrary product codes — they describe the physical weave density and yarn thickness of the glass fabric, which determines both the cured thickness per ply and the electrical properties of the resulting dielectric.

106: Very lightweight, thin (~50–75 μm per cured ply), high resin content (~65–70%), low Dk (~3.8–4.0 for standard epoxy systems). Rarely used alone; sometimes combined with other styles in HDI builds.

1080: Light, thin (~75–100 μm per cured ply), high resin content (~60–65%), Dk typically ~4.0–4.2. Preferred for outer layer dielectrics in impedance-critical designs because its high resin content gives a smoother, more uniform surface and lower, more stable Dk. The right choice when you need thin dielectric spacing and tight impedance control.

2116: Medium weight (~110–130 μm per cured ply), balanced resin content (~50–55%), Dk ~4.2–4.4. The general-purpose workhorse for most inner-layer separation. Good balance of thickness, Dk stability, and cost.

7628: Heavyweight (~180–220 μm per cured ply), lower resin content (~42–46%), Dk ~4.5–4.9. Used where dielectric thickness needs to be maximised efficiently with fewer plies. Lower cost than thinner styles at equivalent thickness. Less suitable for controlled-impedance layers adjacent to high-speed signals because its lower resin content produces a higher, less uniform Dk.

Glass Style Selection Reference

Glass Style	Cured Thickness (per ply)	Resin Content	Dk Range (FR-4 epoxy)	Best Stack-Up Position
106	50–75 μm	~68%	3.8–4.0	HDI build-up, thin spacers
1080	75–100 μm	~65%	4.0–4.2	Outer signal layer dielectrics
2116	110–130 μm	~52%	4.2–4.4	General inner-layer separation
7628	180–220 μm	~44%	4.5–4.9	Thick core, power/GND plane separation

Mixing glass styles within a single stackup is standard practice. The correct approach: use the appropriate glass style for each dielectric position based on the thickness and Dk requirements of that specific layer — not a single glass style for the entire board.

Material Selection Layer by Layer: What Each Layer Type Needs

Outer Signal Layers (L1 and Bottom)

Outer signal layers are where most SMD components mount and where the highest-density routing typically lives. The key requirement for the dielectric beneath the outer copper is tightly controlled Dk and thickness, because this directly determines microstrip impedance for every controlled-impedance trace on that layer.

For standard digital designs below 1 GHz: high-Tg FR-4 core or prepreg (Tg ≥ 170°C) with 1080 or 2116 glass style. For RF and microwave signals above 1 GHz: a low-loss laminate such as Rogers RO4350B, Isola Astra MT77, or Panasonic Megtron 6 for the outer layer dielectric. The impedance calculation must use the specific pressed Dk for the glass style and resin content actually used — not a generic “FR-4 Dk 4.2” assumption.

Outer layer copper weight is typically 1 oz (35 μm) for signal layers in standard designs. For fine-pitch components, ½ oz (18 μm) allows finer etching tolerances. For high-current applications at the outer layer, 2 oz is used but requires adjusted design rules for etchback.

Reference Planes: Ground and Power Planes

Ground planes are the most important single design element in a multilayer stackup for signal integrity. A solid, unbroken copper ground plane adjacent to each signal layer provides the return current path for every trace above it. The material between the signal layer and its adjacent ground plane is the primary impedance-defining dielectric in the entire board.

For the dielectric between signal layer and adjacent ground or power plane: use the best controlled-Dk material your budget allows at your operating frequency. For a sub-1 GHz digital design, standard FR-4 prepreg works well. For a 5 GHz RF layer, specify a low-loss laminate for this specific dielectric spacing. The distance between signal and reference plane (dielectric thickness) is the most important single parameter in impedance calculations — small changes in this dimension translate directly into impedance error.

Power planes should be adjacent to ground planes wherever possible to maximise inter-plane capacitance, which acts as distributed decoupling for power distribution noise. Thin dielectric between power and ground planes (using 1080 or 2116 prepreg rather than 7628) increases this capacitance and improves power delivery network performance.

The material specification for ground and power plane layers is the core that hosts the copper pour. These layers do not have special dielectric requirements beyond the standard IPC-4101 thermal specifications for your assembly process — save the premium material for the signal-adjacent dielectrics.

Inner Signal Layers

Inner signal layers (stripline geometry) are shielded between two reference planes — typically ground-signal-ground or ground-signal-power-signal-ground configurations. The stripline geometry offers inherently better EMI performance than microstrip because the signal is fully enclosed between reference conductors.

For the dielectrics above and below inner signal layers, the same logic applies as for outer layers: use the Dk and thickness appropriate for your target impedance, with the appropriate glass style. For high-speed differential pairs on inner layers above 10 Gbps, specify spread-glass construction to minimise the fiber weave effect — the periodic Dk variation caused by glass bundles and resin pockets creates differential skew that cannot be corrected by equalisation.

Copper weight on inner signal layers is typically ½ oz (18 μm) for signal routing to allow finer trace widths and spacing. For inner power or ground planes, 1 oz or 2 oz is standard depending on current requirements.

Standard Stack-Up Examples with Material Assignments

4-Layer Stack-Up: The Baseline for Most Designs

Layer	Function	Material Type	Glass Style	Copper Weight
L1 (Top)	Signal / Components	Foil on prepreg	1080 × 1	1 oz
Prepreg	L1 to L2 dielectric	Standard FR-4	1080 or 2116	—
L2 (Inner 1)	Ground Plane (GND)	Core (copper pour)	Core embedded	1 oz
Core	L2 to L3 dielectric	High-Tg FR-4 core	2116 or 7628	—
L3 (Inner 2)	Power Plane (PWR)	Core (copper pour)	Core embedded	1 oz
Prepreg	L3 to L4 dielectric	Standard FR-4	1080 or 2116	—
L4 (Bottom)	Signal / Components	Foil on prepreg	1080 × 1	1 oz

The typical 4-layer stackup uses foil construction: prepreg between the outer copper foil and the inner cores, with a single core forming the L2/L3 pair. The central core thickness is adjusted (using a thicker core or thicker prepreg) to hit the target board thickness of 1.6 mm.

Key material decisions: specify high-Tg FR-4 (Tg ≥ 170°C, Td ≥ 340°C) for all layers on any lead-free assembly program. Specify the glass style for the prepreg between L1 and L2, and between L3 and L4 — this is your impedance-defining dielectric for microstrip traces on L1 and L4.

6-Layer Stack-Up: Adding Signal and Shielding Capacity

Layer	Function	Material	Dielectric	Copper
L1 (Top)	Signal (RF/high-speed)	Prepreg on foil	1080 × 1 or 2116 × 1	1 oz
L2	Ground Plane	Core copper pour	—	1 oz
L3	Inner Signal	Core / prepreg	2116 or 1080	½ oz
L4	Inner Signal	Core / prepreg	2116 or 1080	½ oz
L5	Power Plane	Core copper pour	—	1 oz
L6 (Bottom)	Signal (general)	Prepreg on foil	2116 × 1	1 oz

In this 6-layer configuration, L3 and L4 are stripline layers shielded between L2 (GND) and L5 (PWR). The dielectric between L2 and L3, and between L4 and L5, is the impedance-defining dimension for stripline traces on those layers. Placing L3 and L4 symmetrically around the board centre prevents warpage from asymmetric copper distribution.

8-Layer High-Speed Stack-Up

Layer	Function	Notes
L1	Signal (top)	Low-loss laminate if >5 GHz
L2	GND	Adjacent to L1 — impedance reference
L3	Signal (inner)	Stripline, tight to L2 GND
L4	GND	Solid copper pour
L5	PWR	Thin dielectric to L4 GND for capacitance
L6	Signal (inner)	Stripline, tight to L7 GND
L7	GND	Adjacent to L6 and L8
L8	Signal (bottom)	Low-loss if >5 GHz

For high-speed designs above 10 Gbps, the dielectric between each signal layer and its adjacent ground plane should be a low-loss laminate (Df ≤ 0.004 minimum; ≤ 0.002 for 56G+ designs). The inner-layer dielectrics separating non-signal plane pairs can use standard high-Tg FR-4, keeping cost proportional to the performance requirement.

Hybrid Stack-Up Material Selection for Mixed RF and Digital Designs

The hybrid stackup is one of the most practically important and least documented aspects of PCB stack-up laminate material selection. When a board carries both RF signals (above 5 GHz) and digital interfaces, using premium RF material for the entire board is over-specification — and using standard FR-4 for everything fails the RF layers. The hybrid approach uses low-loss material selectively on layers that need it.

A typical 5G radio unit with a 12-layer hybrid stackup might look like this:

L1/L2: Rogers RO4350B core for RF antenna feed and PA output matching — low Df (0.0037), tight Dk tolerance (±0.05), FR-4-compatible processing. RO4450F bonding prepreg at the interface to the next material.

L3–L8: Isola I-Tera MT40 or Panasonic Megtron 6 for high-speed eCPRI digital interfaces and mixed-signal routing — Df ~0.003, adequate for 25G digital interfaces.

L9–L12: High-Tg FR-4 for power planes, ground planes, and low-frequency control layers — economical, thermally adequate, standard fabrication.

The interface between material types requires careful engineering. When bonding Rogers RO4350B to an FR-4 adjacent layer, the bond ply must be Rogers RO4450F prepreg — not standard FR-4 prepreg. Rogers RO4450F is designed for the glass transition temperature, resin flow, and CTE compatibility required at this specific interface. Substituting generic FR-4 prepreg at a Rogers/FR-4 interface is a delamination waiting to happen in thermal cycling.

CTE must be matched across the stackup. Rogers RO4350B has Z-axis CTE of ~46 ppm/°C. Standard FR-4 runs 60–80 ppm/°C. This mismatch is manageable in a hybrid build if the stackup is balanced — an equal number of layers of each material on either side of the board centerline — but an unbalanced hybrid stackup with mismatched CTE will warp during lamination and under thermal cycling.

Ventec PCB laminate ranges offer hybrid-compatible options spanning both standard high-Tg FR-4 and thermally enhanced variants, with application engineering support specifically for multi-material stackup compatibility validation — a useful starting point when a new hybrid construction needs qualification support.

The Symmetry Rule: Why Your Stack-Up Must Be Balanced

Stackup symmetry is the one mechanical requirement that overrides almost all electrical optimisation. An asymmetric stackup — where the top half of the board has different materials, copper weights, or layer thicknesses than the bottom half — generates differential thermal stress during lamination and subsequent reflow, causing the board to warp or twist. Even a well-designed electrical stackup becomes a manufacturing problem if it violates symmetry.

Symmetry means the stackup reads identically from the top down as from the bottom up, mirrored around the board centerline. The same laminate type at the same distance from the center. The same copper weight on symmetric layers. If you use 1080 prepreg between L1 and L2, use 1080 prepreg between L(n-1) and L(n). If your RF layer is L1 on a low-loss laminate, the matched RF layer is L(n) on the same material.

When you need to break symmetry — for example, in a hybrid design where the RF layers must be on L1/L2 without a matching RF layer on L11/L12 — work with your fabricator to verify the board’s bow and twist through lamination simulation before committing to the design. Some fabricators can balance asymmetric builds using copper balancing layers (thin copper sheets added for mechanical symmetry without electrical function), but this adds cost and should be treated as a last resort.

Copper Weight Selection by Layer Function

Copper weight selection is part of stack-up material selection because it directly affects dielectric thickness after etching (heavy copper traces sit higher, compressing more resin during lamination) and controls thermal and electrical performance.

Layer Function	Recommended Copper Weight	Rationale
Outer signal layer (fine-pitch SMD)	½ oz (18 μm)	Fine trace/space; precise etching
Outer signal layer (general)	1 oz (35 μm)	Standard; adequate for most routing
Inner signal layer	½ oz (18 μm)	Fine traces; lower inductance
Inner ground/power plane	1 oz (35 μm)	Good current capacity; standard
Heavy current power plane	2 oz (70 μm) or more	High current; thermal spreading
RF signal layer	1 oz (35 μm)	Standard; consistent etching

Heavy copper inner layers (2 oz+) create a surface topology challenge for prepreg bonding — the prepreg must flow enough resin to fill the deeper valley between etched traces. For 2 oz inner layers, specify High Resin (HR) grade prepreg to ensure adequate resin fill and prevent voids at the trace-dielectric interface.

Material Selection Rules That Prevent the Most Common Stack-Up Failures

Rule 1 — Never specify “FR-4” without a Tg rating for lead-free production. Specify the exact product (Isola 370HR, Shengyi S1000-2M, Nan Ya NPG-170D) or at minimum the Tg (≥170°C) and Td (≥340°C). “FR-4” alone leaves material selection entirely to the fabricator.

Rule 2 — Use the correct Dk for each glass style in impedance calculations. A stackup using 1080 prepreg (Dk ~4.1) above L1 and 7628 core (Dk ~4.7) at the center requires separate impedance calculations for each layer, not a single “FR-4 Dk 4.4” assumption. A 0.3 Dk error at 100 μm dielectric thickness shifts 50Ω microstrip by 3–4Ω — outside most impedance tolerances.

Rule 3 — Always specify two prepreg plies minimum for IPC Class 3 (high-reliability) boards. IPC Class 3 requires minimum dielectric thickness of 2.56 mil (65 μm) with a minimum of two prepreg plies in the laminated section. Single-ply prepreg is susceptible to dielectric voids and is not acceptable for high-reliability applications.

Rule 4 — Specify the bonding prepreg at every hybrid material interface. “Use appropriate adhesive” is not a specification. Name the specific bond ply (RO4450F, RO4450B, or equivalent) at every Rogers/FR-4 interface. Your fabricator needs this information to order material and set lamination parameters.

Rule 5 — Verify stackup symmetry before sending for fabrication. Calculate total copper weight and dielectric type for each half of the stackup, mirrored at the center. If they don’t match, redesign before fabrication — not after receiving warped prototypes.

Useful Resources for PCB Stack-Up Laminate Material Selection

• Sierra Circuits Stackup Designer: Free online tool at protoexpress.com — lets you design stackups layer by layer with material selection, dielectric thickness, and integrated impedance calculation. One of the most practical web-based stackup tools available.
• Isola PCB Stackup Designer: Free at isola-group.com — uses frequency-dependent, resin-content-dependent material models for Isola’s full laminate portfolio. More accurate than generic Dk calculations for controlled-impedance designs.
• Rogers Corporation Stackup and Impedance Calculator: Available at rogerscorp.com — supports hybrid RO4000/FR-4 stackup configurations with material-specific Dk values.
• Siemens Z-planner Enterprise: Advanced stackup tool with 200+ laminate families from multiple manufacturers, using measured frequency-dependent Dk/Df models. The most comprehensive stackup material database commercially available; supported by a free trial.
• IPC-2221 — Generic Standard on Printed Board Design: Available from ipc.org — covers minimum dielectric thickness, design rules for multilayer construction, and via aspect ratio guidelines by IPC class.
• IPC-4101 — Specification for Base Materials for Rigid and Multilayer PCBs: Available from ipc.org — the laminate specification standard with slash sheets defining material classifications. Essential for specifying materials formally on fabrication drawings.
• Polar Instruments Si9000e: Industry-standard impedance field solver supporting full stackup material modelling with copper roughness correction. Used by most professional PCB fabricators for controlled-impedance stackup verification.
• Panasonic Megtron Stackup Selector: Available at na.industrial.panasonic.com — configures high-speed stackups using Megtron 6/7 with glass style options and pressed Dk data for each construction.

5 FAQs on PCB Stack-Up Laminate Material Selection

Q1: How do I decide between foil construction and cap construction for a multilayer board?

Foil construction — where prepreg separates the outer copper foil from the adjacent core — is the industry default and preferred method for the vast majority of multilayer PCBs. It offers better layer-to-layer registration, easier manufacturability, lower cost, and higher yield than cap construction. Cap construction (where a thin core sits as the outer element, sandwiching the prepreg internally) is used only in specific situations: hybrid boards where a specialty laminate core must be on the outer layer, or certain HDI constructions requiring controlled blind via depth. If your fabricator doesn’t raise a specific reason for cap construction, default to foil.

Q2: Why does the fabricator’s impedance number differ from my calculator’s result, even when I use the same Dk?

Three common causes: First, the fabricator uses measured press-out Dk data for their specific lamination cycle on your specific glass style — these differ from the datasheet nominal Dk at 50% resin content. A 2116 prepreg at your fabricator may press to 48% resin content, giving a different Dk than the 50%-referenced datasheet value. Second, copper roughness adds effective Dk at the surface — the rough copper-dielectric interface raises the effective Dk seen by signals in the skin-depth region, typically 0.1–0.3 units above the bulk Dk. Third, trace width tolerance after etching affects the calculated impedance — if your traces are 0.1 mil narrower than target, impedance shifts. Always validate your stackup with the fabricator’s actual pressed-thickness and Dk data before expecting to hit ±5% impedance tolerance.

Q3: Can I use standard FR-4 prepreg to bond Rogers RO4350B cores in a hybrid stackup?

The short answer is no, not reliably. Standard FR-4 prepreg has a higher lamination temperature, different resin flow characteristics, and different CTE than RO4350B. Using it at the Rogers/FR-4 interface risks inadequate bonding, delamination during thermal cycling, and Dk discontinuity at the material boundary. Specify Rogers RO4450F prepreg (or RO4450B for its higher Dk companion) at every Rogers/FR-4 interface. RO4450F is engineered for this specific application — it cures at temperatures compatible with both materials, provides adequate peel strength, and has a CTE that manages the transition. Your total stackup Dk model must include the RO4450F layer as a distinct dielectric element.

Q4: How thin can I make the dielectric between a signal layer and its reference plane?

The practical minimum for standard production is around 75–100 μm (3–4 mils) using two plies of 1080 prepreg. Going thinner is possible with a single ply of 106 prepreg (~50–60 μm), but single-ply prepreg is excluded from IPC Class 3 qualification, and very thin dielectrics are sensitive to voiding and dielectric thickness variation during lamination. Thin dielectrics improve coupling between signal and reference (beneficial for impedance control and EMI), but they also increase crosstalk between adjacent signal layers if those layers aren’t separated by a reference plane. For HDI designs requiring very thin dielectrics, laser-ablated build-up layers with non-woven dielectric films can achieve 25–50 μm spacing reliably, but this requires HDI manufacturing capability.

Q5: Should I specify the exact prepreg glass style on my fabrication drawing, or is “2116 FR-4 prepreg” sufficient?

For impedance-controlled layers, specify the glass style. Write “2116 × 1 ply, Tg ≥ 170°C, Td ≥ 340°C” for a non-critical inner separation. Write “1080 × 2 plies” for a controlled-impedance microstrip dielectric layer where you’ve calculated impedance using 1080 Dk values. If you leave the glass style unspecified and write only a target dielectric thickness, the fabricator will select whatever glass combination achieves that thickness — which may produce a different Dk than you assumed, shifting your impedance outside tolerance. For non-controlled-impedance layers (power/ground separation where exact Dk isn’t critical), specifying only the nominal thickness and minimum Tg is acceptable. Match your specification detail to the sensitivity of each layer’s function.

Conclusion: Build the Stack-Up Before You Start the Layout

The PCB stack-up laminate material selection decision-making process should be completed — including material choice, dielectric thickness per layer, glass style selection, copper weights, and symmetry verification — before placement and routing begin. Trying to retrofit a stackup to an existing layout is invariably more expensive in engineering time than doing it properly at the start.

The discipline to apply across every stackup decision: match the material performance tier to the actual requirement of each layer. Signal-adjacent dielectrics on high-speed RF layers need premium low-loss material. Power plane separations in the board interior need structurally adequate, thermally reliable FR-4. Not every layer needs the same material, and not every board needs premium laminate throughout. The stack-up that performs reliably and costs appropriately is the one that gives each layer exactly what it needs — and nothing more expensive.