ZCU102 Evaluation Kit: Ultimate Zynq UltraScale+ Dev Board

The ZCU102 board has become the go-to development platform for engineers working with Zynq UltraScale+ MPSoC technology. After spending considerable time with this ZCU102 evaluation board across multiple projects, I can confidently say it represents AMD’s most capable general-purpose development kit for heterogeneous computing.

This comprehensive guide covers everything you need to know about the Xilinx ZCU102—from hardware specifications and interface capabilities to practical applications and comparison with alternatives. Whether you’re evaluating the platform for embedded vision, communications, or AI acceleration, this article provides the technical details that matter.

What Makes the Zynq ZCU102 Special

The ZCU102 stands apart from other Zynq UltraScale+ development boards by offering the most comprehensive interface support available. Built around the XCZU9EG-2FFVB1156 MPSoC, this board provides access to nearly every feature the silicon offers.

Core Processing Architecture

The XCZU9EG device at the heart of the ZCU102 board integrates multiple processing domains:

Processing Element	Specifications
Application Processor	Quad-core ARM Cortex-A53 @ 1.5 GHz
Real-Time Processor	Dual-core ARM Cortex-R5F @ 600 MHz
Graphics Processor	Mali-400 MP2 GPU
FPGA Fabric	600K logic cells, 2,520 DSP slices
Block RAM	32.1 Mb
Maximum I/O	328 user I/O

This combination of 64-bit application processors, deterministic real-time cores, and substantial programmable logic makes the Zynq ZCU102 suitable for demanding applications that require both software flexibility and hardware acceleration.

ZCU102 Board Hardware Specifications

Understanding the complete hardware capabilities helps determine whether the ZCU102 evaluation board meets your project requirements.

Memory Architecture

The Xilinx ZCU102 provides separate memory interfaces for the Processing System (PS) and Programmable Logic (PL):

Memory Type	Capacity	Interface	Connected To
DDR4 SODIMM	4 GB	64-bit with ECC	Processing System
DDR4 Component	512 MB	16-bit	Programmable Logic
Quad-SPI Flash	128 MB	Dual x4	Configuration/Storage

The PS-side DDR4 SODIMM socket accepts standard laptop memory modules, allowing upgrades if your application requires more memory. The ECC support is particularly valuable for applications requiring data integrity, such as safety-critical systems or financial computing.

The dedicated PL-side DDR4 provides independent memory bandwidth for FPGA logic, enabling high-throughput data processing without competing with processor memory access.

High-Speed Serial Connectivity

Where the ZCU102 board truly excels is high-speed serial connectivity. The board exposes 24 GTH transceivers capable of 16.3 Gb/s line rates:

Interface	GTH Lanes	Maximum Rate	Connector
FMC HPC0	8	16.3 Gb/s	J5
FMC HPC1	8	16.3 Gb/s	J4
SFP+ Cages	4	10 Gb/s	J9-J12
HDMI	3	6 Gb/s	J6/J7
PCIe	4 (GTR)	8 Gb/s	J1

The dual FMC HPC connectors provide 16 GTH transceivers total, plus 64 user-defined differential I/O signals. This extensive connectivity enables adding specialized daughter cards for applications like software-defined radio, high-speed data acquisition, or multi-channel video processing.

Networking and Communications

The ZCU102 evaluation board supports multiple Ethernet implementations:

Interface	Speed	PHY Type	Connector
RGMII	10/100/1000 Mb/s	TI DP83867	RJ45 (J46)
SGMII	1 Gb/s	Via SFP+	SFP+ Cages
10G Ethernet	10 Gb/s	PL Implementation	SFP+ Cages

The onboard Texas Instruments DP83867IRPAP RGMII PHY connects to PS GEM3 and provides reliable Gigabit Ethernet for development and debugging. For production systems requiring higher bandwidth, the four SFP+ cages support 10G Ethernet using PL-based MAC/PHY implementations.

Display and Video Interfaces

Video capabilities on the Xilinx ZCU102 include:

Interface	Direction	Specifications
DisplayPort	Output	1.2a, up to 4K@30
HDMI	Input/Output	2.0, with retimer
MIPI CSI-2	Input	Via FMC expansion

The DisplayPort output connects directly to the PS hard block, requiring minimal PL resources. HDMI support uses three GTH transceivers with an external retimer to drive output signals at HDMI 2.0 rates.

ZCU102 Board Features and Interfaces

Beyond the core connectivity, the ZCU102 includes numerous features that simplify development.

Configuration Options

Multiple configuration paths support different deployment scenarios:

Boot Mode	Description	Use Case
JTAG	USB-connected debug	Development, debugging
Quad-SPI	Dual x4 flash	Production deployment
SD Card	Full-size slot	Rapid iteration, Linux boot
eMMC	8 GB onboard	Production systems

The boot mode selection via DIP switch SW6 enables quick transitions between development (JTAG/SD) and production (QSPI/eMMC) configurations.

Clock Generation

The ZCU102 board provides sophisticated clocking infrastructure:

Clock Source	Frequency	Purpose
Si570 Programmable	10-810 MHz	User clock, default 156.25 MHz
Si5341 Jitter Attenuator	Multiple outputs	GTH reference clocks
Fixed Oscillators	33.33 MHz, 300 MHz	PS reference, PL user clock

The Si570 programmable oscillator allows software-controlled frequency changes via I2C, valuable for applications requiring different clock domains without hardware modifications.

Power System Architecture

The ZCU102 evaluation board implements a sophisticated power delivery system:

Rail	Voltage	Purpose
VCCINT	0.85V (adjustable)	PL core voltage
VCC_PSINTFP	0.85V	PS core voltage
VCCO_PSDDR	1.2V	PS DDR I/O
VADJ_FMC	1.2V/1.8V/2.5V/3.3V	FMC I/O voltage

The adjustable VCCINT rail supports different speed grades, and VADJ_FMC configuration enables compatibility with various FMC daughter cards.

Power input options include a 12V wall adapter (included) or ATX power connector for integration into larger systems.

System Controller

An onboard TI MSP430 microcontroller manages:

• Power sequencing and monitoring
• Boot mode detection
• PMBUS voltage/current monitoring
• EEPROM data management
• User interface (buttons, LEDs, DIP switches)

The System Controller GUI (BUI) accessible via USB allows real-time monitoring of voltages, currents, and temperatures—invaluable for power optimization work.

Read more Xilinx FPGA Series:

Comparing ZCU102 with Other Evaluation Boards

Choosing between AMD’s Zynq UltraScale+ boards depends on your specific requirements.

ZCU102 vs ZCU104 vs ZCU106

Feature	ZCU102	ZCU104	ZCU106
Device	XCZU9EG	XCZU7EV	XCZU7EV
Logic Cells	600K	504K	504K
Video Codec	No	Yes (H.264/H.265)	Yes (H.264/H.265)
FMC GTH Lanes	16	1	7
SFP+ Ports	4	0	2
PCIe Slot	Yes	No	Yes
Price (approx.)	$2,995	$1,899	$3,570

Choose the ZCU102 when:

• Maximum high-speed I/O is required (16 GTH on FMC)
• Connecting FMC cards with JESD204B or other serial interfaces
• 10G Ethernet via SFP+ is needed
• Largest FPGA fabric is required

Choose the ZCU104 when:

• Hardware video codec (H.264/H.265) is essential
• Embedded vision is the primary application
• Budget is constrained
• Minimal high-speed serial connectivity is acceptable

Choose the ZCU106 when:

• Video codec plus moderate high-speed I/O is needed
• PCIe integration is required
• Balanced feature set at higher price point is acceptable

The ZCU102 lacks the hardware video codec found in EV-variant devices, which matters for applications like 4K video streaming. However, its superior high-speed connectivity makes it the better choice for software-defined radio, high-speed data acquisition, and communications infrastructure development.

Practical Applications for the Xilinx ZCU102

The Zynq ZCU102 serves diverse application domains.

Software-Defined Radio (SDR)

The dual FMC HPC connectors with 16 GTH transceivers enable connecting high-speed ADC/DAC boards like the Analog Devices ADRV9371. Each FMC slot provides eight JESD204B lanes, sufficient for multi-channel radio systems.

A typical SDR configuration:

• FMC HPC0: RF transceiver daughter card
• FMC HPC1: Additional RF front-end or baseband processing
• SFP+: 10G Ethernet backhaul
• PS DDR4: Baseband sample buffers
• PL DDR4: FFT/channelizer coefficient storage

Machine Learning Inference

While the ZCU104/ZCU106 with EV devices target ML more directly, the ZCU102’s larger FPGA fabric supports bigger DPU (Deep Learning Processing Unit) configurations:

DPU Configuration	ZCU102 Support
B4096 Architecture	Yes
Dual DPU Cores	Yes
FINN Overlays	Yes
Vitis AI Models	Full Model Zoo support

The PYNQ framework and DPU-PYNQ package enable rapid ML prototyping with Python and Jupyter notebooks. The larger fabric allows experimenting with custom accelerator architectures beyond standard DPU configurations.

Communications Infrastructure

Network equipment development benefits from the ZCU102’s extensive connectivity:

• 4x SFP+ cages for 10G/25G Ethernet
• PCIe Gen2 x4 root port for NIC testing
• Multiple Gigabit Ethernet paths (RGMII + SGMII)
• Hardware timestamping support

Video Processing Pipeline Development

Despite lacking hardware codec, the ZCU102 board supports video processing:

• HDMI input for video capture
• DisplayPort output for processed video display
• FMC expansion for camera interfaces (MIPI CSI-2)
• Sufficient PL resources for soft video codec implementations

Getting Started with the ZCU102 Evaluation Board

Setting up the Xilinx ZCU102 follows a straightforward process.

Kit Contents

The EK-U1-ZCU102-G kit includes:

• ZCU102 evaluation board
• 12V power supply and cables
• USB cables (Micro-B, Type-A to Micro-B)
• USB 3.0 hub (Targus)
• Ethernet cable
• Vivado Design Suite: Design Edition voucher

Initial Hardware Setup

1. Connect USB Micro-B cable to J83 (JTAG/UART)
2. Connect Ethernet cable to J46 (optional, for Linux networking)
3. Insert SD card with boot image (optional)
4. Set boot mode via SW6 DIP switches
5. Connect 12V power supply to J52
6. Press SW1 power button

Boot Mode Configuration

SW6[4:1]	Boot Mode
0000	JTAG
0010	QSPI32
1110	SD Card
0110	eMMC

For initial development, JTAG mode allows downloading configurations directly from Vivado without preparing boot media.

Running Built-In Self Test

The ZCU102 ships with QSPI programmed for BIST:

1. Set SW6 to QSPI32 mode (0010)
2. Power on the board
3. BIST runs automatically, indicated by LED patterns
4. Connect to System Controller GUI for detailed results

Essential Resources for ZCU102 Development

Official Documentation

Document	Number	Description
User Guide	UG1182	Complete board documentation
Quick Start Guide	XTP426	Initial setup instructions
Schematics	Available on product page	Full board design
Master XDC	Available in Vivado	Pin constraints

Download Links

Resource	URL
Product Page	https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html
Documentation	https://docs.xilinx.com/v/u/en-US/ug1182-zcu102-eval-bd
BSP Downloads	https://www.xilinx.com/support/download.html
Reference Designs	https://github.com/Xilinx
Vivado License	Voucher included with kit

Community Resources

Resource	Description
AMD Adaptive Support	Official technical support
Xilinx Wiki	Application notes, example designs
PYNQ Community	Python productivity examples
GitHub Repositories	Open-source reference designs

ZCU102 Board Design Considerations

When designing systems around the ZCU102, consider these factors.

Power Budget Planning

Component	Typical Power	Notes
PS (Cortex-A53 active)	3-5W	Depends on workload
PL (moderate utilization)	5-15W	Highly design-dependent
DDR4 Memory	2-4W	Access pattern dependent
GTH Transceivers	0.5W per lane	Active lanes only
FMC Cards	10-20W	Varies by card

Plan for 50-60W total system power for demanding applications.

Read more Xilinx Products:

Thermal Management

The ZCU102 evaluation board includes an active heatsink with fan. For high-utilization designs:

• Monitor junction temperature via SYSMON
• Ensure adequate airflow around FMC cards
• Consider additional cooling for enclosed installations

Signal Integrity

For designs using high-speed FMC interfaces:

• Verify FMC card pinout compatibility
• Check VADJ_FMC voltage requirements
• Review GTH reference clock requirements
• Validate timing constraints early in development

Frequently Asked Questions

What is the difference between the ZCU102 and ZCU104?

The ZCU102 uses the XCZU9EG (EG variant) with 600K logic cells and 16 GTH transceivers on FMC connectors, while the ZCU104 uses the XCZU7EV (EV variant) with 504K logic cells, hardware H.264/H.265 video codec, but only 1 GTH on FMC. Choose the ZCU102 for maximum high-speed I/O and larger FPGA fabric; choose the ZCU104 for embedded vision applications requiring hardware video encoding/decoding.

Can I run Linux on the Xilinx ZCU102?

Yes, the ZCU102 fully supports Linux. AMD provides PetaLinux BSPs for rapid Linux development, and the board supports Ubuntu via PYNQ images. The quad-core Cortex-A53 with 4GB DDR4 provides substantial processing capability for Linux-based applications including machine learning inference, video processing, and network applications.

How many FMC cards can I connect to the ZCU102 board?

The ZCU102 has two FMC HPC (High Pin Count) connectors, allowing two FMC daughter cards simultaneously. Each connector provides 8 GTH transceivers and 32 differential I/O pairs. Both connectors conform to VITA 57.1 FMC specification, enabling use of standard FMC cards from various vendors for ADC/DAC, RF, video capture, and other applications.

Is the ZCU102 suitable for production deployment?

The ZCU102 evaluation board is designed primarily for development and prototyping. For production, consider AMD’s System-on-Module (SOM) offerings or design a custom board using the ZCU102 as a reference. The ZCU102 schematics are available for studying power delivery, memory interface, and high-speed signal routing best practices.

What software tools are required for ZCU102 development?

Development requires Vivado Design Suite for hardware design and Vitis for software development. A node-locked, device-locked license voucher is included with the kit. For Linux development, PetaLinux provides the embedded Linux toolchain. Optional tools include Vitis AI for machine learning and PYNQ for Python-based rapid prototyping.

Development Workflow and Best Practices

Working effectively with the ZCU102 board requires understanding the typical development workflow.

Hardware Design Flow

A typical FPGA development sequence for the Xilinx ZCU102:

Stage	Tool	Output
Block Design	Vivado IP Integrator	BD file
Synthesis	Vivado	Netlist
Implementation	Vivado	Placed/Routed design
Bitstream Generation	Vivado	.bit file
Hardware Export	Vivado	.xsa file

The Vivado project should target the xczu9eg-ffvb1156-2-e device (production boards ship with -2 speed grade). Reference the board files for automatic pin constraint population.

Software Development Approaches

Multiple software development paths exist for the ZCU102:

Approach	Use Case	Complexity
Bare-metal	Real-time, deterministic	Medium
FreeRTOS	RTOS applications	Medium
Linux (PetaLinux)	General embedded Linux	Higher
PYNQ (Python)	Rapid prototyping	Lower

For most embedded applications, PetaLinux provides the most productive path. The provided BSP includes drivers for all onboard peripherals, boot configuration, and a working root filesystem.

Debugging Techniques

The ZCU102 evaluation board supports comprehensive debugging:

JTAG Debugging:

• Connect via J83 USB for JTAG access
• Vivado Hardware Manager for FPGA debugging
• Vitis debugger for ARM core debugging
• Supports simultaneous PL and PS debug

Serial Console:

• USB-UART bridge on J83 provides console access
• Default baud rate: 115200
• Multiple UART channels available

ILA (Integrated Logic Analyzer):

• Insert ILA cores during synthesis for real-time signal capture
• Trigger on specific conditions
• Essential for debugging high-speed interfaces

System Monitor:

• Built-in SYSMON provides voltage/temperature monitoring
• Access via JTAG or software APIs
• Critical for thermal debugging

Performance Optimization Tips

Maximizing performance on the Zynq ZCU102 involves several considerations:

Memory Bandwidth:

• Use AXI HP ports for high-bandwidth PL-to-DDR access
• Enable AXI data width conversion for optimal bus utilization
• Consider coherent access via HPC ports when PS/PL share data

Clock Domain Management:

• Use MMCM/PLL for clean clock generation
• Implement proper CDC (Clock Domain Crossing) for multi-clock designs
• Consider asynchronous FIFOs for high-speed interfaces

Power Optimization:

• Gate unused logic with clock enables
• Use block RAM power-down modes when inactive
• Reduce GTH transceiver power when links are idle

Transitioning from ZCU102 to Production

The ZCU102 evaluation board serves as an excellent prototype platform, but production deployment requires additional planning.

Design Migration Considerations

When moving from development to production:

Aspect	ZCU102	Production Consideration
Device Package	FFVB1156	May need different package
Speed Grade	-2	Verify timing at target grade
Memory	SODIMM socket	Soldered components typical
Power	12V input	Custom power architecture

Reference Design Availability

AMD provides several reference designs for the ZCU102 that accelerate development:

• Base TRD (Targeted Reference Design)
• Machine Learning TRD with DPU
• Ethernet reference designs (1G, 10G, 25G)
• DisplayPort/HDMI examples
• PCIe endpoint and root port examples

These designs serve as starting points for custom implementations and demonstrate best practices for Zynq UltraScale+ development.

Documentation for Custom Board Design

The complete ZCU102 schematics provide invaluable reference material for custom board design:

• Power delivery architecture
• DDR4 memory routing
• GTH transceiver layout
• FMC connector implementation
• High-speed signal integrity techniques

Studying these schematics before starting custom hardware design saves significant development time.

Making the Most of Your Zynq ZCU102 Investment

The ZCU102 evaluation board represents a significant investment at approximately $2,995 MSRP. Maximizing its value requires understanding both its strengths and limitations.

Leverage the strengths:

• Use the extensive GTH connectivity for high-speed interface prototyping
• Take advantage of the dual FMC slots for multi-function systems
• Exploit the large FPGA fabric for complex custom IP
• Utilize the comprehensive documentation and reference designs

Work around limitations:

• For video codec requirements, consider soft implementations or the ZCU104
• For cost-sensitive projects, evaluate whether all features are necessary
• For production, plan migration to SOM or custom board early

The Xilinx ZCU102 remains the most capable general-purpose Zynq UltraScale+ development platform available. Its combination of processing power, FPGA resources, and interface flexibility supports virtually any MPSoC development project. Whether you’re building software-defined radio systems, accelerating machine learning inference, or developing next-generation communications equipment, the ZCU102 provides the foundation for successful product development.