ZC706 Evaluation Board: Advanced Zynq Development Platform for High-Speed Applications

When standard embedded development boards fall short on performance, the ZC706 steps up. I’ve worked with numerous Zynq platforms over the years, and the ZC706 board consistently delivers where others can’t—particularly for PCIe interfaces, high-speed serial communications, and applications demanding serious programmable logic resources. This guide walks through everything you need to know about the Xilinx ZC706 evaluation platform.

Why Choose the ZC706 Board Over Other Zynq Platforms

The Zynq ZC706 targets engineers who need more than basic embedded processing. While the ZC702 handles typical embedded workloads well, the ZC706 unlocks capabilities that simply don’t exist on smaller platforms: 16 GTX transceivers, native PCIe Gen2 x4 support, and over 350K logic cells in the programmable fabric.

I’ve selected the ZC706 for projects involving software-defined radio with Analog Devices FMC cards, high-bandwidth video processing pipelines, and PCIe-based data acquisition systems. Each time, the combination of ARM processing and high-speed serial interfaces proved essential.

ZC706 vs ZC702: Key Differences

The XC7Z045 device on the ZC706 is based on Kintex-7 programmable logic fabric, delivering significantly higher performance than the Artix-7 based XC7Z020 found on the ZC702.

ZC706 Board Hardware Specifications

The Xilinx ZC706 packs substantial hardware into its full-size form factor. Understanding the complete specification helps you determine if this platform fits your project requirements.

Complete ZC706 Specifications Table

Onboard Connectivity

GTX Transceivers: The ZC706’s Defining Feature

The 16 GTX transceivers distinguish the ZC706 from entry-level Zynq boards. These high-speed serial interfaces enable protocols that simply aren’t possible on platforms without dedicated transceivers.

GTX Quad Allocation on ZC706

Each GTX channel supports line rates from 500 Mbps to 12.5 Gbps, making protocols like JESD204B, Aurora, SATA, and 10G Ethernet readily achievable. The Si5324 jitter attenuator provides clean recovered clocks essential for CPRI and OBSAI applications.

Supported High-Speed Protocols

The GTX transceivers on the Zynq ZC706 enable these industry-standard protocols:

PCIe Development on the ZC706 Board

One of the primary reasons engineers select the ZC706 board is native PCIe support. The four-lane Gen2 interface connects directly to GTX Quad 112, providing up to 20 Gbps of bidirectional bandwidth.

PCIe Hardware Configuration

The ZC706 implements PCIe as an endpoint, though root complex configurations are also possible. Key hardware details:

The PCIe reference design demonstrates video processing where 1080p60 streams transfer between a host PC and the ZC706 through the PCIe link. At 4 Gbps for full HD video, significant bandwidth remains for additional data channels.

PCIe Development Steps

Getting PCIe running on the Xilinx ZC706 requires both hardware and software coordination:

1. Hardware Setup: Install the ZC706 in a PC chassis with PCIe slot, connect 12V power
2. Vivado Design: Instantiate AXI PCIe IP core configured for endpoint mode
3. Driver Development: Create Linux PCIe driver for the custom endpoint
4. DMA Configuration: Set up scatter-gather DMA for efficient transfers

The Xilinx-provided PCIe TRD (Targeted Reference Design) offers a starting point, demonstrating register access and DMA transfers between host and device.

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FMC Expansion Capabilities

The ZC706 provides both high-pin-count (HPC) and low-pin-count (LPC) FMC connectors, enabling extensive I/O expansion.

FMC Connector Comparison

The HPC connector supports demanding FMC cards like the AD-FMCOMMS series for software-defined radio or high-speed ADC/DAC evaluation boards. The eight GTX lanes on the HPC connector enable JESD204B interfaces to multi-gigasample converters.

Popular FMC Cards for ZC706

Boot Mode Configuration for the Xilinx ZC706

The ZC706 supports multiple boot sources controlled by DIP switch SW11. Proper configuration prevents frustrating debug sessions.

SW11 Boot Mode Settings

For development, JTAG mode allows direct programming and debug. Production systems typically boot from QSPI for reliability or SD card for easy updates.

JTAG Chain Configuration (SW4)

The default SW4=01 setting routes JTAG through the onboard Digilent USB module, providing both programming and debug capability through a single USB connection.

Memory Architecture on the Zynq ZC706

The dual memory system on the Zynq ZC706 provides flexibility for complex applications requiring both processor and logic-side memory access.

PS-Side DDR3 Component Memory

The Processing System connects to 1 GB of DDR3 component memory through dedicated pins:

This memory serves as the primary system memory for Linux or bare-metal applications running on the ARM cores.

PL-Side DDR3 SODIMM

The Programmable Logic has independent access to 1 GB of SODIMM memory:

This PL-accessible memory enables large frame buffers, lookup tables, or data buffers without consuming PS memory bandwidth. Video processing applications particularly benefit from dedicated PL memory.

Development Environment Setup

Getting started with the ZC706 requires proper tool installation and board configuration.

Required Software Components

Vivado includes the ZC706 board definition files, enabling automatic configuration of PS settings, pin constraints, and peripheral connections when creating new projects.

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First Hardware Design

Create a basic ZC706 project in Vivado:

1. Launch Vivado and select Create Project
2. Choose RTL Project
3. In Default Part, select Boards tab
4. Filter for “ZC706” and select the evaluation board
5. Create Block Design and add ZYNQ7 Processing System
6. Run Block Automation to apply board presets

The board automation configures DDR3 timing, MIO assignments, and clock frequencies specific to the ZC706 hardware.

Built-In Self-Test (BIST) Procedures

The ZC706 includes comprehensive BIST functionality for hardware verification.

BIST Coverage

Run BIST before starting development to confirm board functionality. The test loads from QSPI when SW11 is configured appropriately.

BIST Setup Steps

1. Set SW11 to JTAG mode (00000)
2. Connect USB cables to JTAG (J2) and UART (J17)
3. Open terminal at 115200 baud, 8N1
4. Power on with SW1
5. Program BIST bitstream through Vivado Hardware Manager
6. Observe test results on serial console and LEDs

Power System Architecture

The ZC706 implements sophisticated power management essential for the high-performance XC7Z045 device.

Power Rail Summary

The TI UCD90120A power sequencer manages rail startup/shutdown sequences. The XADC provides real-time voltage and temperature monitoring through software-accessible registers.

Thermal Considerations

The XC7Z045 in high-utilization designs generates significant heat. Monitor junction temperature through XADC and ensure adequate airflow when operating with demanding workloads. The commercial grade device specifies 0-85°C junction temperature range.

Useful Resources and Downloads

Essential documentation and tools for ZC706 development:

Download Links

Frequently Asked Questions

What license is required for ZC706 development?

The XC7Z045 device requires a Vivado license beyond the free WebPACK edition. AMD provides a device-locked license with the ZC706 kit, or you can use a 30-day evaluation license. Some features like partial reconfiguration require additional licensing.

Can the ZC706 function as a PCIe root complex?

Yes, though the default configuration is endpoint mode. Root complex operation requires specific IP configuration and is useful for applications where the ZC706 initiates transactions to attached PCIe devices rather than responding to a host PC.

How do I connect external reference clocks for GTX?

The SMA connectors USER_SMA_CLOCK_P/N accept external differential reference clocks for GTX Quad 111. Ensure your clock source provides appropriate voltage levels matching the bank VCCO setting. The Si5324 can also generate jitter-attenuated clocks from recovered data streams.

What’s the maximum achievable GTX line rate on the ZC706?

The GTX transceivers support up to 12.5 Gbps line rate, suitable for 10G Ethernet and high-speed JESD204B interfaces. Actual achievable rates depend on channel quality, reference clock jitter, and protocol overhead. Always run IBERT tests to verify link quality before deploying production designs.

Can I use ZC702 designs on the ZC706?

Designs require modification due to different devices and pinouts. The ZC706 uses XC7Z045 (FFG900 package) while ZC702 uses XC7Z020 (CLG484 package). PS-side designs often port with minimal changes, but PL designs need constraint updates. The larger device on ZC706 accommodates all ZC702 logic with room to spare.

Troubleshooting Common ZC706 Issues

Years of working with the ZC706 have revealed common pitfalls and their solutions.

JTAG Connection Problems

If Vivado Hardware Manager fails to detect the board:

PCIe Link Training Failures

PCIe issues often stem from hardware configuration:

1. Check J19 jumper: Verify lane width matches your IP configuration
2. Verify reference clock: PCIe requires 100 MHz from the edge connector
3. Confirm power: PCIe auxiliary power may be required for some host systems
4. Review LTSSM: Use Vivado ILA to monitor link training state machine

GTX Eye Diagram Issues

Poor signal integrity on GTX channels indicates:

• Incorrect TX pre-emphasis or post-emphasis settings
• Reference clock jitter exceeding specifications
• Improper termination on external connections
• PCB via stubs or impedance discontinuities on FMC cards

Run IBERT designs to characterize channel quality before deploying production firmware.

Conclusion

The ZC706 evaluation board delivers capabilities essential for demanding embedded applications. The combination of dual ARM Cortex-A9 processors with 350K logic cells, 16 GTX transceivers, and native PCIe support creates a platform suited for high-bandwidth video processing, software-defined radio, industrial automation, and research applications.

For engineers whose projects exceed the capabilities of entry-level Zynq boards, the Xilinx ZC706 provides the headroom needed without stepping up to UltraScale+ platforms. The investment pays dividends in reduced design iterations and access to high-speed interfaces unavailable on smaller devices.

Whether you’re implementing JESD204B links to high-speed converters, developing PCIe accelerator cards, or building systems requiring extensive programmable logic, the Zynq ZC706 offers a proven platform with comprehensive tool support and extensive community resources.