Xilinx TRD (Targeted Reference Designs): Complete Getting Started Guide

When I first received a ZCU102 evaluation board, I made the classic mistake of trying to build everything from scratch. After spending two weeks wrestling with boot configurations and video pipeline drivers, a colleague pointed me to Xilinx TRD packages. What took me weeks to accomplish poorly, the Targeted Reference Design got running in an afternoon. If you’re working with Zynq UltraScale+ MPSoC boards and want to accelerate your development, understanding Xilinx TRD resources will save you countless hours.

What Is a Xilinx TRD?

A Xilinx TRD (Targeted Reference Design) is a complete, working design package that demonstrates specific capabilities of AMD/Xilinx evaluation boards. Unlike bare-bones examples that show a single IP block in isolation, TRDs integrate multiple hardware and software components into functional systems that you can boot, run, and extend for your own applications.

Each Xilinx TRD package typically includes Vivado hardware design files with IP Integrator block diagrams, PetaLinux Board Support Packages (BSP) for building Linux images, pre-built SD card images for immediate testing, source code for applications and drivers, and comprehensive documentation with step-by-step tutorials. The beauty of these reference designs is that they’re fully supported by AMD and updated with each major tool release. When you encounter issues, the Xilinx Community Forums have active discussions specifically tagged for TRD troubleshooting.

Available Xilinx TRD Types for Zynq UltraScale+

AMD maintains several TRD variants targeting different application domains. Here’s an overview of the primary options:

ZCU102 TRD: The Base Reference Design

The ZCU102 TRD serves as the foundational reference design for Zynq UltraScale+ MPSoC development. It demonstrates the heterogeneous processing capabilities of the device across the Application Processing Unit (APU), Real-Time Processing Unit (RPU), and Programmable Logic (PL).

The ZCU102 TRD supports multiple video input sources including HDMI Rx, MIPI CSI-2 Rx for camera sensors, USB webcam, and an internal Test Pattern Generator. For outputs, you get both DisplayPort Tx and HDMI Tx pipelines. The design includes hardware-accelerated 2D convolution filters and optical flow processing that you can toggle between software and hardware implementations to understand the performance benefits of PL acceleration.

What makes the ZCU102 TRD particularly educational is its modular structure. The design is broken into ten Design Modules (DM1 through DM10) that progressively build complexity. DM1 covers basic SMP Linux on the APU, DM2 adds FreeRTOS on RPU0, DM3 implements bare-metal performance monitoring on RPU1, and subsequent modules combine these elements with video pipelines and accelerators.

ZCU106 TRD: Video Codec Unit Reference Design

If your application involves video encoding or decoding, the ZCU106 TRD is where you need to start. The ZCU106 board features the Zynq UltraScale+ EV device variant, which includes a hardened Video Codec Unit (VCU) capable of simultaneous H.264/H.265 encoding and decoding at 4K resolution and 60 frames per second.

The ZCU106 TRD demonstrates the VCU capabilities through multiple design modules covering different use cases. You’ll find configurations for HDMI capture and display, MIPI camera input, SDI interfaces for broadcast applications, and even PCIe-based transcoding where the ZCU106 acts as an accelerator card in a host system.

The software stack in the ZCU106 TRD uses GStreamer as the multimedia framework, with OpenMAX IL integration for the VCU encoder and decoder elements. This architecture lets you construct video pipelines using familiar GStreamer command-line tools or the provided Qt-based GUI application.

Read more Xilinx FPGA Series:

Best Zynq UltraScale+ Development Boards Compared (2024)

How to Install Vivado on Windows 11: Step-by-Step Tutorial

Spartan-3E FPGA Board: Beginner Tutorial & Project Ideas

Where to Buy Xilinx FPGAs: Complete Authorized Distributors Guide

Xilinx Alveo Accelerator Cards: Data Center FPGA Guide

Xilinx AMD Acquisition: What It Means for FPGA Developers

Xilinx Artix-7 FPGA Family: Features, Specs & Selection Guide

Xilinx Artix-7 FPGA Price Guide

Xilinx CPLD Programmer and Xilinx CPLD Board: The Complete Guide for Engineers

Xilinx FPGA Programming for Beginners: First Project Tutorial

Xilinx JTAG Programming: Complete Hardware Setup & Debug Tutorial

Xilinx Kintex-7 FPGA: Mid-Range Performance Powerhouse

Xilinx Spartan-3 FPGA: Legacy Support & Migration Guide

Xilinx Spartan-6 FPGA: Still Relevant? Complete 2025 Guide

Xilinx Spartan-7 FPGA: Low-Cost Solution for Embedded Design

Xilinx Virtex-7 FPGA: High-End Performance for Critical Applications

Getting Started with Your First Xilinx TRD

Let me walk through the practical steps to get a TRD running on your board. I’ll use the ZCU106 VCU TRD as the example since video codec applications are common, but the process is similar for other TRDs.

Step 1: Download the TRD Package

Navigate to the evaluation kit documentation page for your board on the AMD website. For the ZCU106, this is the “Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit” product page. Under the Documentation & Designs tab, you’ll find the TRD download link. The package filename follows a pattern like rdf0428-zcu106-vcu-trd-2022-1.zip where the version number matches your Vivado/PetaLinux tool version.

After downloading, extract the archive to a working directory. I recommend using a path without spaces since some build scripts can have issues with spaces in paths.

Step 2: Understand the Package Structure

The TRD package has a consistent directory organization:

The images directory is your fast path to a working system. The pl and apu directories contain everything needed to rebuild the design from source if you need to customize it.

Step 3: Prepare the SD Card

Format an SD card with a FAT32 partition (most cards come this way). Copy the pre-built image files from the appropriate design module folder. For the basic VCU TRD, you need BOOT.BIN (contains FSBL, U-Boot, PMU firmware, and bitstream), image.ub (Linux kernel and device tree), and any application binaries or configuration files specified in the documentation.

Step 4: Configure Board Connections

The ZCU106 TRD board setup requires several connections. Set the boot mode switches (SW6) for SD card boot, typically with switches in the ON-OFF-OFF-OFF position. Connect the micro USB cable to J83 for UART console access. Insert the prepared SD card into slot J100. Connect your display via DisplayPort (U129) or HDMI (P7). For video input designs, connect your source to the appropriate HDMI Rx or attach an FMC camera module to the FMC connector.

Step 5: Boot and Run

Connect power (12V to the 6-pin Molex connector) and open a terminal emulator configured for 115200 baud, 8N1. You should see boot messages as the system initializes. Once Linux boots, the TRD applications are typically available in the root filesystem.

For the VCU TRD, you can run the command-line GStreamer application with configuration files that specify your desired pipeline:

vcu_gst_app /media/card/config/1-4kp60/Display/Single_4kp60_AVC_HIGH.cfg

This launches a 4K60 H.264 encoding pipeline displaying to HDMI output.

Building the Xilinx TRD from Source

While pre-built images get you started quickly, real projects require customization. Here’s how to rebuild TRD components.

Rebuilding the Hardware Platform

The Vivado project can be regenerated from TCL scripts included in the pl directory. Source your Vivado installation and run the provided Makefile or TCL script. The build process creates a block design using IP Integrator, connects the processing system to PL peripherals, and generates a hardware handoff file (XSA) for software development.

For the ZCU106 VCU TRD, expect the Vivado build to take one to two hours depending on your workstation specifications. The resulting XSA file feeds into the PetaLinux build.

Rebuilding the Software Platform

PetaLinux builds consume the hardware XSA and produce bootable Linux images. The TRD includes a BSP file that pre-configures kernel options, device tree settings, and root filesystem contents for the reference design.

Create a new PetaLinux project from the BSP, configure it with your rebuilt XSA if you modified the hardware, and run the build. The output includes all boot components ready for SD card deployment.

Design Module Dependencies in ZCU102 TRD

The ZCU102 Base TRD uses a dependency structure where advanced modules build upon simpler ones. Understanding this helps when customizing.

If you only need video functionality without the RPU demonstrations, you can work with DM5 or DM8/DM9 without dealing with the multi-processor complexity of the full DM10 design.

Read more Xilinx Products:

XCVU35P-L2FSVH2104E: AMD Virtex UltraScale+ HBM FPGA Specifications, Features & Applications

XCVU35P-1FSVH2892E: High-Performance AMD Virtex UltraScale+ HBM FPGA

XC2C256-7FT256I CoolRunner-II CPLD: High-Performance Programmable Logic Device

XC2C128-7VQ100C: High-Performance CoolRunner-II CPLD for Advanced Digital Design

XC18V01SO20I: High-Performance Configuration PROM for FPGA Applications

XQ18V04VQ44N: Military-Grade 4Mbit FPGA Configuration PROM by AMD Xilinx

XC18V02VQG44I: Complete Guide to Xilinx 2Mbit In-System Programmable Configuration PROM

XC18V02PC44C0936: AMD Xilinx 2Mbit In-System Programmable Configuration PROM for FPGA Applications

XC2C512-7FT256C: AMD Xilinx CoolRunner-II CPLD | 512 Macrocell Programmable Logic Device

XC17S30PC: Xilinx Spartan OTP Configuration PROM for FPGA Applications

Useful Resources for Xilinx TRD Development

Common Issues and Troubleshooting

Through my own TRD experiences and monitoring the forums, certain issues appear repeatedly.

HDMI monitors sometimes fail to link at the expected resolution. The TRD may default to HDMI 1.4 mode (30fps at 4K) instead of HDMI 2.0 (60fps). Check dmesg output for messages about the DP159 retimer configuration. Power cycling the monitor often resolves initial link failures.

Memory allocation errors in the GUI application typically indicate the video source is in an incompatible state. Power cycle any connected HDMI sources to ensure they’re outputting standard formats before launching TRD applications.

SDSoC accelerator performance varies dramatically between Debug and Release builds. Always use Release configuration (-O3 optimization) for performance testing.

Frequently Asked Questions

What Vivado version should I use with a specific TRD release?

TRD packages are tightly coupled to specific tool versions. The package filename includes the version (e.g., 2022.1), and you must use matching Vivado and PetaLinux versions. Mixing versions causes compatibility issues with IP cores and BSP configurations.

Can I use ZCU106 TRD designs on ZCU102?

The boards have different device variants (EV vs. CG/EG), different I/O configurations, and different peripheral implementations. While software concepts transfer, the hardware designs require significant modification. Use the TRD specifically created for your board.

How do I add custom IP to a TRD hardware design?

Open the regenerated Vivado project, modify the block design to include your IP, update constraints if needed, and rebuild the XSA. You’ll then need to update device tree entries and potentially add Linux drivers to the PetaLinux configuration.

Are TRD designs production-ready?

TRDs are reference implementations intended for evaluation and as starting points. They demonstrate functionality but may not be optimized for power consumption, resource utilization, or specific performance targets. Production designs typically require significant customization.

Where can I get technical support for TRD issues?

Start with the Xilinx Community Forums, searching for existing threads before posting new topics. Include your TRD version, tool versions, and specific error messages. The Xilinx Answers Database also contains solutions to known issues. For deeper engagement, contact your AMD FAE.

Conclusion

Xilinx TRD packages represent years of engineering effort distilled into accessible reference designs. Whether you’re evaluating Zynq UltraScale+ capabilities, prototyping a video application, or learning the platform, these Targeted Reference Designs provide working examples that demonstrate best practices for hardware/software integration.

The ZCU102 TRD gives you a comprehensive platform for understanding heterogeneous processing with video pipelines. The ZCU106 TRD delivers everything needed for serious video codec development. Both include the source code, scripts, and documentation to take you from running pre-built images to building fully customized systems.

Start with the pre-built images to verify your hardware setup, then progressively dig into the build flows as your project requirements demand customization. The modular design module approach lets you focus on exactly the functionality you need without getting overwhelmed by the complete system complexity.