Contact Sales & After-Sales Service

Contact & Quotation

  • Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.
  • Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.
Drag & Drop Files, Choose Files to Upload You can upload up to 3 files.

Notes:
For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.

CoolRunner-II CPLD Family: Ultra Low-Power Logic Solutions

Battery-powered designs present unique challenges that traditional CPLDs simply cannot address. When your product runs on coin cells or harvested energy, every microamp counts. The Xilinx CoolRunner-II family was built specifically for these scenarios, delivering programmable logic with standby currents measured in microamps rather than milliamps.

Having worked with both CoolRunner-II and XC9500XL devices across various projects, the power difference is substantial. The XC9572XL might draw 18mA at 20MHz, while a similarly-configured XC2C32A stays under 1mA. For handheld instruments, remote sensors, and wearable electronics, that difference determines whether your design runs for hours or weeks.

This guide covers the complete CoolRunner-II family from the tiny XC2C32A through the Xilinx XC2C256 and beyond, helping you select the right device and implement power-efficient designs.

What Makes CoolRunner-II Different?

The CoolRunner-II family represents Xilinx’s second-generation low-power CPLD architecture, combining the speed characteristics of the XC9500 series with the ultra-low power consumption of the XPLA3 family. Built on 0.18-micron CMOS technology with a 1.8V core, these devices achieve what other CPLD families cannot: true zero standby power operation.

Traditional CPLDs use sense amplifier architectures that draw continuous current even when idle. The CoolRunner-II employs Fast Zero Power (FZP) technology, using cascaded CMOS gates instead of sense amplifiers. This fundamental architectural change eliminates the residual current that plagues competing solutions.

The result is standby current as low as 16µA typical, with total standby power around 28.8µW. For battery-operated equipment, this translates directly into extended operational life without compromising performance when active.

CoolRunner-II Family Overview

DeviceMacrocellsSystem GatesMax I/OTPD (ns)Max Frequency
XC2C32A32750333.8323 MHz
XC2C64A641,500644.6263 MHz
XC2C1281283,0001005.7244 MHz
XC2C2562566,0001845.7256 MHz
XC2C3843849,0002407.1217 MHz
XC2C51251212,0002707.1179 MHz

XC2C32A: The Smallest CoolRunner-II

The XC2C32A packs 32 macrocells into packages as small as 5mm x 5mm (QFG32). This makes it ideal for space-constrained applications where even a few square millimeters matter.

Despite its compact size, the XC2C32A delivers impressive performance with 3.8ns pin-to-pin delays and system frequencies up to 323MHz. Two function blocks provide the logic resources, while 33 I/O pins handle external connectivity.

XC2C32A Package Options

PackagePinsUser I/ODimensions
QFG3232215mm x 5mm
VQG4444337mm x 7mm
CPG5656336mm x 6mm

Common applications for the XC2C32A include keypad controllers, simple state machines, clock generation, and voltage level translation in mobile devices.

Xilinx XC2C64A: The Popular Mid-Range Choice

The Xilinx XC2C64A has become the go-to device for engineers entering CoolRunner-II development. With 64 macrocells organized in four function blocks, it offers enough logic density for moderate designs while maintaining excellent power efficiency.

At around $2-3 in quantity, the XC2C64A delivers exceptional value. The device supports up to 64 I/O pins depending on package selection, with pin-to-pin delays as low as 4.6ns. Available development boards from Digilent and others make prototyping straightforward.

XC2C64A Key Specifications

ParameterValue
Macrocells64
Function Blocks4
System Gates1,500
Max I/O64
I/O Banks2
Global Clocks3
TPD (fastest grade)4.6 ns
Max System Frequency263 MHz
Standby Current< 100 µA

The Xilinx XC2C64A comes in multiple packages including VQ44 (44-pin VQFP), VQ100 (100-pin VQFP), CP56 (56-ball CSP), and QF48 (48-pin QFN). This variety lets you optimize for either minimum board space or maximum I/O count.

XC2C128: Stepping Up Logic Density

When 64 macrocells aren’t quite enough, the XC2C128 doubles the logic capacity while maintaining the same 5.7ns timing performance as the larger family members. Eight function blocks provide 128 macrocells and up to 100 I/O pins.

The XC2C128 introduces several features not available in smaller devices:

  • Clock Division: Built-in clock divider supporting division by 2, 4, 6, 8, 10, 12, 14, and 16
  • DataGATE: Power-saving input blocking capability
  • Additional I/O Standards: HSTL and SSTL support for memory interfaces

XC2C128 Package Options

PackagePinsUser I/O
VQ10010080
TQ144144100
CP132132100

Read more Xilinx FPGA Series:

Xilinx XC2C256: High-Density Low-Power Logic

The Xilinx XC2C256 represents the sweet spot for designs requiring substantial logic resources without sacrificing power efficiency. With 256 macrocells providing 6,000 system gates, this device handles complex state machines, protocol converters, and multi-function glue logic.

Sixteen function blocks deliver the processing power, while up to 184 I/O pins support wide bus interfaces. The 5.7ns pin-to-pin delay matches the XC2C128, ensuring consistent timing across the mid-range family members.

XC2C256 Specifications

ParameterValue
Macrocells256
Function Blocks16
System Gates6,000
Max I/O184
I/O Banks2
Product Terms/Macrocell56
TPD5.7 ns
TSU2.4 ns
TCO4.5 ns
Max System Frequency256 MHz
Quiescent Current13 µA typical

XC2C256 Package Selection

PackagePinsUser I/OBest For
VQ10010080Compact designs
TQ144144118General purpose
CP132132106High-density PCB
PQ208208173Maximum I/O
FT256256184High-pin-count BGA

Read more Xilinx Products:

CoolRunner-II Architecture Deep Dive

Understanding the internal architecture helps you write efficient designs and predict resource utilization accurately.

Function Blocks and Macrocells

Each CoolRunner-II function block contains 16 macrocells connected to a 40-input, 56-product-term PLA (Programmable Logic Array). The Advanced Interconnect Matrix (AIM) routes signals between function blocks with minimal power consumption.

Every macrocell can access up to 56 product terms, providing exceptional logic density without product term stealing from neighbors. This differs from older CPLD architectures where complex functions required borrowing resources from adjacent cells.

Power-Saving Features

CoolRunner-II devices include several mechanisms to minimize power consumption:

DataGATE Technology (XC2C128 and larger): Allows selective blocking of input signals during idle periods. When inputs don’t switch, dynamic power drops to near zero. A latch captures the input state when blocked, maintaining logic consistency.

CoolCLOCK: Combines clock division with DualEDGE flip-flops to reduce effective clock frequency while maintaining throughput. This can cut clock-related power consumption by 50%.

DualEDGE Registers: Flip-flops that trigger on both clock edges, effectively doubling data rate without doubling clock frequency.

Multi-Voltage I/O Banking

The XC2C32A, XC2C64A, XC2C128, and XC2C256 support two independent I/O banks. Each bank can operate at different voltage levels (1.5V, 1.8V, 2.5V, or 3.3V), simplifying level translation between different voltage domains on your board.

Larger devices (XC2C384 and XC2C512) provide four I/O banks, supporting up to four different voltage levels simultaneously.

CoolRunner-II Feature Comparison

FeatureXC2C32AXC2C64AXC2C128XC2C256XC2C384XC2C512
I/O Banks222244
Clock DivisionNoNoYesYesYesYes
DataGATENoNoYesYesYesYes
DualEDGEYesYesYesYesYesYes
HSTL SupportNoNoYesYesYesYes
SSTL SupportNoNoYesYesYesYes
Schmitt InputsYesYesYesYesYesYes

Power Supply Requirements

CoolRunner-II devices require multiple supply voltages, which adds complexity compared to single-supply CPLDs like the XC9500XL.

Voltage Rails

SupplyVoltage RangePurpose
VCCINT1.7V to 1.9VCore logic
VCCIO11.4V to 3.6VI/O Bank 1
VCCIO21.4V to 3.6VI/O Bank 2
VCCAUX3.0V to 3.6VJTAG interface

For simplest power design, connect VCCIO1 and VCCIO2 to the same 3.3V rail and use a 1.8V regulator for VCCINT. VCCAUX can share the 3.3V supply.

Decoupling Guidelines

Each VCCINT pin requires a 100nF ceramic capacitor placed within 5mm. VCCIO pins need similar treatment. Use 0.1µF X7R or better dielectric for optimal high-frequency performance.

Programming CoolRunner-II Devices

All CoolRunner-II devices support IEEE 1149.1/1532 JTAG programming. The four JTAG pins (TCK, TMS, TDI, TDO) provide in-system programming capability without removing the device from your board.

Development Tools

Xilinx ISE WebPack: The primary development environment, supporting design entry, synthesis, implementation, and programming. While older than Vivado, ISE remains the required tool for CoolRunner-II development.

Programming Hardware Options:

ProgrammerNotes
Xilinx Platform Cable USBOfficial solution, native ISE support
Digilent HS2/HS3Reliable alternative
FT2232-based cablesBudget option via SVF playback
UrJTAGOpen-source SVF programmer

Programming Sequence

  1. Create design using Verilog, VHDL, or schematic entry
  2. Define pin constraints in UCF file
  3. Synthesize and implement design
  4. Generate JEDEC programming file
  5. Connect JTAG programmer to target
  6. Program device using iMPACT or compatible tool

Programming endurance exceeds 1,000 cycles for CoolRunner-II devices (compared to 10,000 for XC9500XL). For designs requiring frequent reprogramming during development, this limit rarely becomes a concern.

CoolRunner-II vs XC9500XL: Which to Choose?

The choice between CoolRunner-II and XC9500XL depends on your application priorities.

CriteriaCoolRunner-IIXC9500XL
Standby Power< 100 µASeveral mA
Core Voltage1.8V3.3V
5V ToleranceNoYes
Supply ComplexityMultiple railsSingle 3.3V
Programming Cycles1,000+10,000+
CostSlightly higherLower
SpeedModerateFaster

Choose CoolRunner-II when:

  • Battery operation or energy harvesting
  • Multi-voltage system interfaces (1.5V to 3.3V)
  • Heat dissipation constraints
  • Portable or wearable applications

Choose XC9500XL when:

  • 5V system compatibility needed
  • Simple power supply preferred
  • Maximum speed required
  • Cost is primary concern

Typical Applications for CoolRunner-II

The ultra-low power characteristics make CoolRunner-II devices ideal for specific application categories.

Portable and Battery-Operated Equipment

Handheld instruments, medical devices, remote sensors, and wearable electronics benefit most from CoolRunner-II power efficiency. The instant-on capability (no configuration time) suits applications requiring immediate response from sleep states.

Voltage Level Translation

With two or four I/O banks operating at independent voltages, CoolRunner-II devices serve as intelligent level shifters. Unlike passive translators, you can add logic functions (filtering, timing adjustment, protocol conversion) to the translation path.

Wireless Interface Controllers

Bluetooth modules, WiFi subsystems, and RF transceivers often require glue logic running from battery power. CoolRunner-II handles control sequencing while minimizing drain on limited energy budgets.

Low-Power State Machines

Industrial sensors, building automation controllers, and environmental monitors spend most of their time idle, waking periodically to collect and transmit data. CoolRunner-II’s near-zero standby consumption suits this duty cycle perfectly.

Useful Resources for CoolRunner-II Development

Documentation Downloads

DocumentDescription
DS090CoolRunner-II Family Datasheet
DS310XC2C32A Device Datasheet
DS311XC2C64A Device Datasheet
DS093XC2C128 Device Datasheet
DS094XC2C256 Device Datasheet
XAPP389CoolRunner-II Power Calculation
XAPP399Interfacing to High-Speed SSTL

Development Boards

BoardDeviceFeatures
Digilent CoolRunner-II StarterXC2C256Pmod ports, switches, LEDs
Dangerous Prototypes BreakoutXC2C64AMinimal, low-cost
Seeed Studio CPLD BoardXC2C64AUSB programming, breadboard-friendly

Software Tools

ToolPurpose
ISE WebPack 14.7Design entry, synthesis, implementation
iMPACTDevice programming
XPower AnalyzerPower estimation

FAQs About CoolRunner-II CPLDs

What is the main advantage of CoolRunner-II over other CPLDs?

The primary advantage is ultra-low power consumption. CoolRunner-II devices draw as little as 16µA standby current compared to several milliamps for traditional CPLDs like XC9500XL. This makes them suitable for battery-powered applications where other CPLDs would drain batteries too quickly. The Fast Zero Power technology eliminates the residual current that sense-amplifier-based CPLDs always draw.

Can CoolRunner-II interface with 5V logic?

No, CoolRunner-II devices are not 5V tolerant. Maximum input voltage is 3.9V (for LVCMOS33). If you need 5V compatibility, use the XC9500XL family instead, or add external level shifters. The CoolRunner-II multi-voltage I/O banks support 1.5V, 1.8V, 2.5V, and 3.3V interfaces natively.

Which CoolRunner-II device should I start with?

The Xilinx XC2C64A offers an excellent balance of capability and cost for learning and prototyping. It provides 64 macrocells, enough for meaningful projects, while remaining affordable ($2-3 each). Development boards based on this device cost under $20 and include necessary programming support.

Are CoolRunner-II devices still available for new designs?

AMD (which acquired Xilinx) issued an End of Life notice for CoolRunner-II in early 2024, with final orders accepted through mid-2024. While devices remain available through distribution channels, new designs should consider alternative solutions. Existing products can source devices from distributors’ stock for continued production.

How does the power consumption compare at operating frequency?

At 20MHz operating frequency, an XC9500XL might draw approximately 18mA while a similarly-loaded CoolRunner-II stays under 1mA. The difference becomes even more dramatic at standby, where CoolRunner-II draws microamps versus milliamps for competing CPLDs. For battery life calculations, this order-of-magnitude improvement often determines project feasibility.

Conclusion

The CoolRunner-II family carved out a unique niche in programmable logic by prioritizing power efficiency without completely sacrificing performance. From the tiny XC2C32A through the Xilinx XC2C256 and larger devices, these CPLDs enabled battery-powered designs that traditional programmable logic couldn’t support.

While the product family has reached end-of-life status, existing designs can continue sourcing devices from distribution. For new projects requiring similar ultra-low power characteristics, consider modern alternatives like Lattice MachXO3 or evaluate whether your application truly needs the power optimization CoolRunner-II provides.

For legacy designs or projects where CoolRunner-II devices remain available, the combination of instant-on operation, multi-voltage I/O banking, and micro-amp standby current continues to deliver value in power-constrained applications.

Leave a Reply

Your email address will not be published. Required fields are marked *

Contact Sales & After-Sales Service

Contact & Quotation

  • Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.

  • Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.

Drag & Drop Files, Choose Files to Upload You can upload up to 3 files.

Notes:
For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.