Xilinx CPLD Guide: XC9500, CoolRunner & Applications

The Xilinx CPLD families have defined programmable logic for over two decades, providing engineers with reliable, non-volatile solutions for glue logic, interface bridging, and system control applications. From the original Xilinx XC9500 5V devices to the low-power CoolRunner series, these CPLDs have found their way into countless industrial, automotive, and consumer products.

Having designed dozens of boards using Xilinx XC9500XL devices for microprocessor interfaces and bus conversion, I can attest to their reliability and ease of use. This guide covers the complete Xilinx CPLD portfolio, architecture details, programming methods, and practical application considerations—including the recent end-of-life announcements that affect long-term design decisions.

Understanding Xilinx CPLD Architecture

A Xilinx CPLD consists of multiple Function Blocks (FBs) interconnected by a programmable switch matrix. Unlike FPGAs that require external configuration at power-up, CPLDs store their configuration in non-volatile Flash memory and are ready to operate immediately after power is applied.

Core Architectural Components

Every Xilinx CPLD shares these fundamental building blocks:

Component	Function	Key Features
Function Blocks (FBs)	Programmable logic	18 macrocells per block, 36 inputs
Macrocells	Logic implementation	D/T flip-flops, combinatorial bypass
I/O Blocks (IOBs)	External interface	Slew rate control, bus hold
FastCONNECT Matrix	Signal routing	Full interconnect between all FBs
JTAG Controller	Programming/test	IEEE 1149.1 boundary scan

Function Block Architecture

Each Function Block in a Xilinx XC9500 or Xilinx XC9500XL device provides substantial logic capability:

Feature	XC9500	XC9500XL/XV
Inputs from Matrix	36	54
Macrocells	18	18
Product Terms Total	90	90
Product Terms per Macrocell	5 direct	5 direct
Clock Sources	3 global + 1 PT	3 global + 1 PT
Output Enables	Global + PT	Global + PT

The wider 54-input fan-in on Xilinx XC9500XL devices provides superior routability and reduces fitting failures when designs approach full utilization.

Xilinx XC9500 Family: The 5V Standard

The original Xilinx XC9500 family established Xilinx’s position in the CPLD market, offering 5V operation with industry-leading performance for its time.

Xilinx XC9500 Device Options

Device	Macrocells	Usable Gates	Registers	Max I/O	tPD (ns)
XC9536	36	800	36	34	5
XC9572	72	1,600	72	72	5
XC95108	108	2,400	108	108	7.5
XC95144	144	3,200	144	133	7.5
XC95216	216	4,800	216	166	10
XC95288	288	6,400	288	192	15

Xilinx XC9500 Key Features

The Xilinx XC9500 series introduced several innovations:

Feature	Specification
Core Voltage	5V
I/O Compatibility	3.3V and 5V tolerant
Programming	5V ISP via JTAG
Endurance	10,000 program/erase cycles
Data Retention	20 years minimum
fCNT Maximum	125 MHz
Output Drive	24 mA

These devices remain popular in legacy systems requiring 5V logic levels and direct interfacing with older microprocessors and bus standards.

Xilinx XC9500XL Family: 3.3V High Performance

The Xilinx XC9500XL family brought lower voltage operation and improved performance while maintaining compatibility with the original architecture.

Xilinx XC9500XL Device Specifications

Device	Macrocells	Usable Gates	Max I/O	tPD (ns)	fSYSTEM (MHz)
XC9536XL	36	800	36	5	178
XC9572XL	72	1,600	72	5	178
XC95144XL	144	3,200	117	5	178
XC95288XL	288	6,400	192	7.5	151

Xilinx XC9500XL Advantages Over XC9500

The Xilinx XC9500XL offered several improvements:

Feature	XC9500	Xilinx XC9500XL
Core Voltage	5V	3.3V
I/O Voltage	5V/3.3V	3.3V/2.5V (5V tolerant inputs)
FB Input Width	36	54
System Frequency	125 MHz	178-200 MHz
Power Consumption	Higher	~50% reduction
Package Options	Limited	Extended including CSP

The 5V-tolerant inputs on Xilinx XC9500XL devices made them ideal for mixed-voltage systems, bridging between 5V legacy components and newer 3.3V logic.

Xilinx XC9500XL Package Options

Package	XC9536XL	XC9572XL	XC95144XL	XC95288XL
44-pin PLCC	34 I/O	34 I/O	–	–
44-pin VQFP	34 I/O	34 I/O	–	–
48-pin CSP	36 I/O	–	–	–
64-pin VQFP	–	52 I/O	–	–
100-pin TQFP	–	72 I/O	81 I/O	–
144-pin TQFP	–	–	117 I/O	117 I/O
208-pin PQFP	–	–	–	168 I/O

XC9500XV: 2.5V Operation

The XC9500XV series extended the family to 2.5V core operation for lower power applications:

Feature	XC9500XL	XC9500XV
Core Voltage	3.3V	2.5V
I/O Banks	Single	Multiple
I/O Voltages	3.3V, 2.5V	3.3V, 2.5V, 1.8V
tPD	5-7.5 ns	4-6 ns
Power	Low	Lower

CoolRunner XPLA3: Ultra-Low Power

The CoolRunner XPLA3 family introduced true zero-power standby operation using a pure CMOS architecture without sense amplifiers.

CoolRunner XPLA3 Device Options

Device	Macrocells	Max I/O	tPD (ns)	Standby Current
XCR3032XL	32	36	5	< 100 µA
XCR3064XL	64	52	5	< 100 µA
XCR3128XL	128	80	5	< 100 µA
XCR3256XL	256	164	7.5	< 100 µA
XCR3384XL	384	220	10	< 100 µA
XCR3512XL	512	260	12	< 100 µA

XPLA3 Architecture Differences

Feature	XC9500XL	CoolRunner XPLA3
Architecture	PAL-based	PLA-based
Standby Power	mA range	µA range
Flip-Flop Types	D, T	D, T, Latch
Clock Sources	4	8
Voltage	3.3V	3.3V
ZIA Inputs	54	40

CoolRunner-II: Best of Both Worlds

The CoolRunner-II combined the high speed of Xilinx XC9500XL with the ultra-low power of XPLA3.

CoolRunner-II Device Specifications

Device	Macrocells	Gates	Max I/O	tPD (ns)	fSYSTEM (MHz)
XC2C32A	32	750	33	3.8	323
XC2C64A	64	1,500	64	4.6	263
XC2C128	128	3,000	100	5.7	244
XC2C256	256	6,000	184	5.7	244
XC2C384	384	9,000	240	6.2	217
XC2C512	512	12,000	270	6.7	179

CoolRunner-II Key Features

Feature	Specification
Core Voltage	1.8V
I/O Voltages	1.5V, 1.8V, 2.5V, 3.3V
Standby Power	16 µA typical
Quiescent Power	28.8 µW
DataGATE	Input isolation for power saving
AIM	Advanced Interconnect Matrix
Design Clock	Up to 323 MHz

CoolRunner-II Unique Features

The DataGATE feature deserves special attention for battery-powered applications:

DataGATE Function	Benefit
Input Isolation	Stops switching on unused inputs
Dynamic Control	Software-controlled input gating
Power Reduction	Eliminates toggle current
Selective Application	Per-input configuration

Read more Xilinx Products:

Xilinx CPLD Applications

The Xilinx CPLD families serve diverse application requirements:

Common Application Areas

Application	Typical Device	Key Requirement
Glue Logic	XC9536XL	Low cost, small footprint
Bus Interface	XC9572XL	5V tolerance, speed
Address Decode	XC95144XL	Many inputs, fast response
FPGA Configuration	CoolRunner-II	Low power, small size
Power Sequencing	XC2C32A	Reliability, low power
Protocol Conversion	XC95288XL	Logic capacity
Clock Management	XC9572XL	Multiple clock domains
I/O Expansion	XC2C64A	Many I/O pins

Microprocessor Interface Design

One of the most common uses for a Xilinx CPLD is bridging between processors and peripherals:

Interface Function	Implementation
Address Decoding	Product term equations
Wait State Generation	State machine
Bus Width Conversion	Registered multiplexing
Interrupt Priority	Combinatorial logic
DMA Control	Sequential logic

FPGA Configuration Controller

CPLDs excel at managing FPGA boot sequences:

Configuration Task	CPLD Role
Power Sequencing	Enable supply rails in order
Clock Generation	Provide stable configuration clock
Flash Interface	Read configuration from SPI/parallel flash
Mode Selection	Set FPGA boot mode pins
Monitoring	Watch DONE and INIT_B signals

Programming Xilinx CPLDs

All Xilinx CPLD families support in-system programming through JTAG.

JTAG Interface Signals

Signal	Function	Direction
TCK	Test Clock	Input
TMS	Test Mode Select	Input
TDI	Test Data In	Input
TDO	Test Data Out	Output

Programming Tools and Cables

Tool/Cable	Purpose	Notes
Xilinx Platform Cable USB	Production programming	Direct USB connection
Digilent JTAG-HS2	Development	Lower cost alternative
iMPACT	ISE-based programming	Included with ISE
Vivado Hardware Manager	Modern programming	Limited CPLD support
OpenOCD	Open source	Community supported

Design Flow for Xilinx CPLDs

Step	Tool	Output
Design Entry	ISE Project Navigator	HDL or schematic
Synthesis	XST	NGC netlist
Fitting	CPLDFit	JED file
Timing Analysis	TRACE	Timing report
Programming	iMPACT	Programmed device

End-of-Life Status and Alternatives

AMD announced the discontinuation of all Xilinx CPLD families in January 2024, with a last-time-buy deadline of June 29, 2024.

Affected Product Families

Family	Status	Last Order Date
Xilinx XC9500XL	Discontinued	June 29, 2024
XC9500XV	Discontinued	June 29, 2024
CoolRunner XPLA3	Discontinued	June 29, 2024
CoolRunner-II	Discontinued	June 29, 2024

Migration Options

For new designs, consider these alternatives:

Original Device	Alternative	Vendor	Notes
Xilinx XC9500XL	ATF15xx	Microchip	Pin-compatible options
XC9572XL	ATF1502AS	Microchip	Similar architecture
XC95144XL	ATF1504AS	Microchip	64-128 macrocells
CoolRunner-II	MAX V	Intel	Non-volatile CPLD
Any CPLD	MAX 10	Intel	Small FPGA alternative
Any CPLD	iCE40	Lattice	Ultra-low power FPGA

ATF15xx as XC9500XL Replacement

The Microchip ATF15xx family provides the closest migration path:

Feature	Xilinx XC9500XL	ATF15xx
Architecture	PAL-based	PAL-based
Macrocells	36-288	32-128
Voltage	3.3V	3.3V/5V options
ISP	JTAG	JTAG
Tools	ISE	WinCUPL, Quartus
Availability	EOL	Active production

Development Tools and Software

Xilinx ISE WebPACK

The free ISE WebPACK supports all Xilinx CPLD devices:

ISE Version	Windows Support	Notes
14.7	Windows 7/10	Last version
14.7 VM	Linux VM	Official virtual machine

ISE WebPACK includes:

Component	Function
Project Navigator	Design management
XST	Synthesis
CPLDFit	Device fitting
TRACE	Timing analysis
iMPACT	Programming
ISim	Simulation

Design Entry Options

Method	Format	Best For
Schematic	.sch	Simple designs
Verilog	.v	Behavioral logic
VHDL	.vhd	Complex state machines
ABEL	.abl	Legacy designs

Essential Resources

Official Documentation

Document	Content
DS063	XC9500 Family Datasheet
DS054	Xilinx XC9500XL Family Datasheet
DS049	XC9500XV Family Datasheet
DS012	CoolRunner XPLA3 Datasheet
DS090	CoolRunner-II Datasheet
UG500	CPLD User Guide

Download Links

Resource	URL
ISE 14.7 WebPACK	https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html
CPLD Datasheets	https://docs.amd.com
Application Notes	https://www.xilinx.com/support/documentation-navigation/design-hubs.html

Frequently Asked Questions

What is the difference between Xilinx XC9500 and Xilinx XC9500XL?

The Xilinx XC9500 operates at 5V core voltage and is designed for legacy 5V systems. The Xilinx XC9500XL operates at 3.3V with 5V-tolerant inputs, offers wider function block inputs (54 vs 36), higher system frequencies (178 MHz vs 125 MHz), and lower power consumption. For new designs before EOL, the Xilinx XC9500XL was the preferred choice due to its improved performance and mixed-voltage capability.

Are Xilinx CPLDs still available for purchase?

AMD discontinued all Xilinx CPLD families with a last-time-buy date of June 29, 2024. While distributor stock may still be available, these devices are no longer manufactured. For new designs, consider alternatives like Microchip ATF15xx CPLDs or Intel MAX V/MAX 10 devices. For existing products, securing lifetime-buy quantities before stock depletes is critical.

How do I program a Xilinx CPLD?

All Xilinx CPLD devices support in-system programming via the JTAG interface using four signals: TCK, TMS, TDI, and TDO. You can use Xilinx Platform Cable USB or compatible third-party programmers with iMPACT software (included in ISE WebPACK). The programming process involves connecting the JTAG header, detecting the device chain, and loading the .jed file generated by the design tools. Programming typically takes seconds and can be performed with the device installed on the PCB.

What is the best replacement for the XC9572XL?

The Microchip ATF1502AS provides the closest architectural match to the XC9572XL, offering similar PAL-based architecture and JTAG programming. For designs requiring more macrocells, the ATF1504AS (64 macrocells) or ATF1508AS (128 macrocells) are available. Intel MAX V CPLDs offer another alternative with different tooling. If willing to migrate to FPGA, the Lattice iCE40 or Intel MAX 10 families provide small, low-cost options with non-volatile configuration storage.

Can I use Vivado to design for Xilinx CPLDs?

No. Vivado does not support Xilinx CPLD devices. You must use ISE Design Suite (version 14.7 is the last release) for all Xilinx XC9500, Xilinx XC9500XL, and CoolRunner designs. ISE WebPACK is available as a free download and includes full CPLD support. While ISE is legacy software, it runs on Windows 7, Windows 10 (32-bit mode), and Linux. Xilinx also provides a virtual machine image with ISE pre-installed for modern systems.

PCB Design Considerations for Xilinx CPLDs

Successful Xilinx CPLD implementation requires attention to several PCB design factors.

Power Supply Requirements

Family	VCCINT	VCCIO	Decoupling
Xilinx XC9500	5V ±5%	5V/3.3V	100nF per VCC pair
Xilinx XC9500XL	3.3V ±5%	3.3V/2.5V	100nF per VCC pair
XC9500XV	2.5V ±5%	Multi-bank	100nF per VCC pair
CoolRunner-II	1.8V ±5%	Multi-bank	100nF + 10µF bulk

JTAG Header Layout

A standard 2×7 or 2×5 header provides programming access:

Pin	Signal	Notes
1	VCC	Optional, for cable power
2	GND	Signal ground reference
3	TCK	Route with matched length
4	GND	Ground shield
5	TDO	Output from CPLD
6	GND	Ground shield
7	TMS	Mode select
8	GND	Ground shield
9	TDI	Input to CPLD
10	GND	Ground shield

Signal Integrity Guidelines

Guideline	Recommendation
Trace Length	< 6 inches for > 100 MHz signals
Series Termination	22-33Ω for fast edges
Decoupling Placement	Within 0.5 inch of VCC pins
Ground Plane	Unbroken under CPLD
I/O Grouping	Keep related signals together

Unused Pin Handling

Approach	Implementation	When to Use
Output Low	Drive to GND in design	Default choice
Output High	Drive to VCC in design	Pull-up loads
Input with Pull	External resistor	Future expansion
Tri-state	Configured as input	Not recommended

Proper handling of unused pins prevents noise coupling and ensures reliable operation across temperature ranges.

Conclusion: Planning for the Future

The Xilinx CPLD families served the industry well for over two decades, with the Xilinx XC9500 and Xilinx XC9500XL becoming de facto standards for glue logic and interface applications. The CoolRunner series pushed power boundaries, enabling battery-powered programmable logic in portable devices.

With AMD’s discontinuation of these products, engineers face important decisions. For existing products in production, securing adequate inventory through authorized channels is essential. For new designs, migration to alternative CPLDs like Microchip’s ATF15xx family or small FPGAs like Intel MAX 10 or Lattice iCE40 represents the path forward.

The architectural concepts proven in Xilinx CPLD designs—macrocell-based logic, product term allocation, and JTAG programming—remain relevant across alternative platforms. Skills developed with these devices transfer readily to modern programmable logic, ensuring the knowledge base built around Xilinx CPLDs continues to provide value even as the silicon itself transitions to end-of-life status.