Quick Presets

Layer Assignment (10 Signal + 5 GND + 5 PWR)
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 GND
L7 SIG
L8 PWR
L9 SIG
L10 GND
L11 PWR
L12 SIG
L13 GND
L14 SIG
L15 PWR
L16 SIG
L17 GND
L18 SIG
L19 PWR
L20 SIG

Copper Layers (20)

Prepreg Layers (10)

Core Layers (9)

Total Board Thickness
3.500mm
3500 µm
vs 3.5mm
+0 µm
Copper (20L)
700 µm
Prepreg (10L)
1310 µm
Core (9L)
1600 µm
10
Signal
5
GND
5
PWR
8
Stripline
2
Microstrip

Stackup Visualization

SOLDER MASK (TOP)
L1 – Top SignalSIG 35µm
PP1 114µm
L2 – GNDGND 35µm
Core 1 100µm
L3 – SignalSIG 35µm
PP2 114µm
L4 – PWRPWR 35µm
Core 2 200µm
L5 – SignalSIG 35µm
PP3 114µm
L6 – GNDGND 35µm
Core 3 200µm
L7 – SignalSIG 35µm
PP4 114µm
L8 – PWRPWR 35µm
Core 4 200µm
L9 – SignalSIG 35µm
PP5 (Center) 185µm
L10 – GND (Center)GND 35µm
Core 5 (Center) 200µm
L11 – PWR (Center)PWR 35µm
PP6 185µm
L12 – SignalSIG 35µm
Core 6 200µm
L13 – GNDGND 35µm
PP7 114µm
L14 – SignalSIG 35µm
Core 7 200µm
L15 – PWRPWR 35µm
PP8 114µm
L16 – SignalSIG 35µm
Core 8 200µm
L17 – GNDGND 35µm
PP9 114µm
L18 – SignalSIG 35µm
Core 9 100µm
L19 – PWRPWR 35µm
PP10 114µm
L20 – Bottom SignalSIG 35µm
SOLDER MASK (BOTTOM)
Outer SIG
Inner SIG
GND
PWR
Prepreg
Core
💡 20L Targets
3.2mm: High-density HDI
3.5mm: Standard 20L
4.0-4.5mm: Server/HPC
5.0mm+: Backplane
📐 Impedance
Microstrip: L1→L2, L20→L19
Stripline: All inner SIG
Center: L10↔L11 tightly coupled
⚡ Power Integrity
5 GND: Distributed ref planes
5 PWR: Multi-rail support
L10-L11: Ultra-low Z decoupling
🔌 Applications
HPC: GPU/TPU accelerators
Network: 400G+ switches
Server: Multi-socket CPU
🔧 20-Layer Design Strategy
10 Signal Layers: L1, L3, L5, L7, L9, L12, L14, L16, L18, L20 — Ultra-high routing density for complex BGA fanout (0.3mm pitch), HBM3 memory, 224G PAM4 / 112G NRZ SerDes, and PCIe Gen6.
5 GND Planes: L2, L6, L10, L13, L17 — Ground reference within 4 layers of every signal; L10 center GND provides symmetry axis and shielding.
5 PWR Planes: L4, L8, L11, L15, L19 — Support 6+ voltage rails with splits (VCore, VIO, VDDA, VDDQ, VPP, VCCSA); L10-L11 form ultra-low-inductance decoupling pair.
Via Strategy: Requires sequential lamination with blind/buried vias and microvias (stacked or staggered); via aspect ratio typically 12:1 max.
Material: Consider low-loss materials (Megtron 6/7, Tachyon, I-Tera MT40) for high-speed lanes >25Gbps.
Symmetry: Structure symmetric about Core 5 center for optimal CTE matching, warpage control (<0.5%), and reliable BGA/LGA reflow.