Quick Presets

Layer Assignment (10 Signal + 4 GND + 4 PWR)
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 GND
L7 SIG
L8 PWR
L9 SIG
L10 SIG
L11 GND
L12 SIG
L13 PWR
L14 SIG
L15 GND
L16 SIG
L17 PWR
L18 SIG

Copper Layers (18)

Prepreg Layers (9)

Core Layers (8)

Total Board Thickness
3.200mm
3200 µm
vs 3.2mm
+0 µm
Copper (18L)
630 µm
Prepreg (9L)
1211 µm
Core (8L)
1400 µm
10
Signal Layers
4
GND Planes
4
PWR Planes
8
Stripline

Stackup Visualization

SOLDER MASK (TOP)
L1 – Top SignalSIG 35µm
PP1 114µm
L2 – GNDGND 35µm
Core 1 100µm
L3 – SignalSIG 35µm
PP2 114µm
L4 – PWRPWR 35µm
Core 2 200µm
L5 – SignalSIG 35µm
PP3 114µm
L6 – GNDGND 35µm
Core 3 200µm
L7 – SignalSIG 35µm
PP4 114µm
L8 – PWRPWR 35µm
Core 4 200µm
L9 – SignalSIG 35µm
PP5 (Center) 185µm
L10 – SignalSIG 35µm
Core 5 200µm
L11 – GNDGND 35µm
PP6 114µm
L12 – SignalSIG 35µm
Core 6 200µm
L13 – PWRPWR 35µm
PP7 114µm
L14 – SignalSIG 35µm
Core 7 200µm
L15 – GNDGND 35µm
PP8 114µm
L16 – SignalSIG 35µm
Core 8 100µm
L17 – PWRPWR 35µm
PP9 114µm
L18 – Bottom SignalSIG 35µm
SOLDER MASK (BOTTOM)
Outer SIG
Inner SIG
GND
PWR
Prepreg
Core
💡 18L Targets
2.8mm: High-density
3.2mm: Standard 18L
3.5-4.0mm: Server/HPC
4.5mm+: Backplane
📐 Impedance
Microstrip: L1→L2, L18→L17
Stripline: All inner SIG
Center pair: L9↔L10
⚡ Power
4 PWR planes: Multi-rail
4 GND planes: Low-Z ref
Symmetric: Balanced CTE
🔌 Applications
Server: CPU/GPU boards
Network: Switch/router
AI/HPC: Accelerators
🔧 18-Layer Design Strategy
10 Signal Layers: L1, L3, L5, L7, L9, L10, L12, L14, L16, L18 — Maximum routing density for complex BGA fanout (0.35mm pitch), DDR5, PCIe Gen5/6, and 224G PAM4 SerDes.
4 GND Planes: L2, L6, L11, L15 — Distributed ground at ~4-layer intervals minimizes return path inductance and provides excellent EMI shielding.
4 PWR Planes: L4, L8, L13, L17 — Support 5+ voltage rails; consider split planes for VCore, VIO, VDDA, VDDQ, etc.
Center Pair: L9-L10 share PP5 — ideal for broadside-coupled differential pairs (100Ω diff) or critical high-speed memory buses.
Via Structure: Consider blind/buried vias and microvias for HDI; via aspect ratio typically 10:1 max for standard drilling.
Symmetry: Structure is symmetric about PP5 center for optimal CTE matching, warpage control (<0.75%), and reliable BGA reflow.