Quick Presets

Layer Assignment (8 Signal + 4 GND + 4 PWR)
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 GND
L7 SIG
L8 PWR
L9 GND
L10 SIG
L11 PWR
L12 SIG
L13 GND
L14 SIG
L15 PWR
L16 SIG

Copper Layers (16)

Prepreg Layers (8)

Core Layers (7)

Total Board Thickness
2.800mm
2800 µm
vs 2.8mm
+0 µm
Copper (16L)
560 µm
Prepreg (8L)
1142 µm
Core (7L)
1200 µm
8
Signal Layers
4
GND Planes
4
PWR Planes
6
Stripline

Stackup Visualization

SOLDER MASK (TOP)
L1 – Top SignalSIG 35µm
PP1 114µm
L2 – GNDGND 35µm
Core 1 100µm
L3 – SignalSIG 35µm
PP2 114µm
L4 – PWRPWR 35µm
Core 2 200µm
L5 – SignalSIG 35µm
PP3 114µm
L6 – GNDGND 35µm
Core 3 200µm
L7 – SignalSIG 35µm
PP4 185µm
L8 – PWRPWR 35µm
Core 4 (Center) 200µm
L9 – GNDGND 35µm
PP5 185µm
L10 – SignalSIG 35µm
Core 5 200µm
L11 – PWRPWR 35µm
PP6 114µm
L12 – SignalSIG 35µm
Core 6 200µm
L13 – GNDGND 35µm
PP7 114µm
L14 – SignalSIG 35µm
Core 7 100µm
L15 – PWRPWR 35µm
PP8 114µm
L16 – Bottom SignalSIG 35µm
SOLDER MASK (BOTTOM)
Outer SIG
Inner SIG
GND
PWR
Prepreg
Core
💡 Common 16L Targets
2.4mm: High-density HDI
2.8mm: Standard 16L
3.2mm: Server/networking
3.5-4.0mm: Backplanes, AI/HPC
📐 Impedance Zones
Microstrip: L1→L2, L16→L15
Stripline: L3,5,7,10,12,14
Tightly-coupled: L8↔L9 center
⚡ Power Integrity
4 PWR planes: Multiple voltage domains
L8-L9: Low-inductance decoupling
Symmetric: Balanced thermal
🔧 16-Layer Design Strategy
8 Signal Layers: L1, L3, L5, L7, L10, L12, L14, L16 — Maximum routing density for complex BGA fanout (0.4mm pitch+), DDR4/5, PCIe Gen4/5, and 112G SerDes.
4 GND Planes: L2, L6, L9, L13 — Distributed ground reference every 4 layers minimizes return path inductance and provides EMI shielding.
4 PWR Planes: L4, L8, L11, L15 — Support multiple voltage rails (VCore, VIO, VDDA, etc.); L8-L9 form tightly-coupled power/ground pair for superior decoupling.
Signal Integrity: Every signal layer has an adjacent reference plane within 0.1-0.2mm for controlled impedance. Inner signal layers (L3,5,7,10,12,14) are fully shielded striplines.
Symmetry: Structure is symmetric about Core 4 center axis for optimal CTE matching, warpage control, and reflow reliability.