Quick Presets

Layer Assignment (8 Signal + 4 GND + 2 PWR)
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 GND
L7 SIG
L8 SIG
L9 GND
L10 SIG
L11 PWR
L12 SIG
L13 GND
L14 SIG

Copper Layers (14)

Prepreg Layers (7)

Core Layers (6)

Total Board Thickness
2.400mm
2400 µm
vs 2.4mm
+0 µm
Copper (14L)
490 µm
Prepreg (7L)
983 µm
Core (6L)
1000 µm

Stackup Visualization

SOLDER MASK (TOP)
L1 – Top SignalSIG 35µm
PP1 114µm
L2 – GNDGND 35µm
Core 1 100µm
L3 – SignalSIG 35µm
PP2 114µm
L4 – PWRPWR 35µm
Core 2 200µm
L5 – SignalSIG 35µm
PP3 114µm
L6 – GNDGND 35µm
Core 3 200µm
L7 – SignalSIG 35µm
PP4 (Center) 185µm
L8 – SignalSIG 35µm
Core 4 200µm
L9 – GNDGND 35µm
PP5 114µm
L10 – SignalSIG 35µm
Core 5 200µm
L11 – PWRPWR 35µm
PP6 114µm
L12 – SignalSIG 35µm
Core 6 100µm
L13 – GNDGND 35µm
PP7 114µm
L14 – Bottom SignalSIG 35µm
SOLDER MASK (BOTTOM)
Outer Signal
Inner Signal
GND Plane
PWR Plane
Prepreg
Core
💡 Common 14-Layer Targets
2.0mm: High-density HDI/BGA breakout
2.4mm: Standard 14L (most common)
2.8-3.2mm: Server, networking, AI accelerators
3.5mm+: Backplanes, heavy copper designs
📐 Impedance Reference
Microstrip: L1→L2, L14→L13
Stripline: L3, L5, L7, L8, L10, L12
Dual-stripline: L7↔L8 center pair
⚡ 14-Layer Design Strategy
8 Signal Layers: L1, L3, L5, L7, L8, L10, L12, L14 — Maximum routing density for complex BGA fanout and high-speed interfaces.
4 GND Planes: L2, L6, L9, L13 — Distributed ground reference at regular intervals minimizes return path lengths.
2 PWR Planes: L4, L11 — Symmetric power distribution; add splits for multiple voltage domains.
Center Pair: L7-L8 share PP4 — ideal for broadside-coupled differential pairs or high-speed memory routing.
Symmetry: Structure is symmetric about PP4 center for optimal thermal expansion and warpage control.