Quick Presets

Layer Assignment
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 SIG
L7 GND
L8 SIG
L9 PWR
L10 SIG

Copper Layers

Prepreg Layers (5)

Core Layers (4)

Total Board Thickness
1.600mm
1600 µm
vs 1.6mm
+0 µm
Copper (10L)
350 µm
Prepreg (5L)
642 µm
Core (4L)
600 µm

Stackup Visualization

SOLDER MASK (TOP)
L1 – Top SignalSIG 35µm
Prepreg 1 (PP1) 114µm
L2 – GND PlaneGND 35µm
Core 1 (FR-4) 100µm
L3 – Inner SignalSIG 35µm
Prepreg 2 (PP2) 114µm
L4 – PWR PlanePWR 35µm
Core 2 (FR-4) 200µm
L5 – Inner SignalSIG 35µm
Prepreg 3 (PP3) – Center 185µm
L6 – Inner SignalSIG 35µm
Core 3 (FR-4) 200µm
L7 – GND PlaneGND 35µm
Prepreg 4 (PP4) 114µm
L8 – Inner SignalSIG 35µm
Core 4 (FR-4) 100µm
L9 – PWR PlanePWR 35µm
Prepreg 5 (PP5) 114µm
L10 – Bottom SignalSIG 35µm
SOLDER MASK (BOTTOM)
Outer Signal
Inner Signal
GND Plane
PWR Plane
Prepreg
Core
💡 Common 10-Layer Targets
1.2mm: High-density mobile, FPGA applications
1.6mm: Standard multilayer (most common)
2.0mm: Industrial, server boards
2.4mm – 3.0mm: Backplanes, heavy copper
⚡ 10-Layer Design Strategy
Symmetric Structure: L1-L5 mirrors L6-L10 for balanced warpage control.
High-Speed Routing: L3, L5, L6, L8 are stripline layers with excellent shielding.
Power Integrity: Distributed GND (L2, L7) and PWR (L4, L9) minimize loop inductance.
📐 Impedance Reference
L1 & L10: Microstrip (ref: L2, L9)
L3: Stripline (ref: L2 + L4)
L5 & L6: Broadside-coupled stripline
L8: Stripline (ref: L7 + L9)