The XCKU095-2FFVB1760I is a high-performance Field Programmable Gate Array (FPGA) from AMD Xilinx, belonging to the Kintex UltraScale family. Built on a 20nm process node, this device delivers an industry-leading blend of signal processing capability, high-speed connectivity, and power efficiency — making it one of the most sought-after mid-range FPGAs for demanding applications. Whether you’re designing for 100G networking, advanced DSP processing, medical imaging, or wireless infrastructure, the XCKU095-2FFVB1760I provides the performance and flexibility your system demands.
Explore the full range of compatible solutions on Xilinx FPGA to find the right device for your project.
What Is the XCKU095-2FFVB1760I?
The XCKU095-2FFVB1760I is a member of the Xilinx Kintex UltraScale FPGA family, designed to maximize price/performance/watt at the 20nm technology node. The part number breaks down as follows:
| Part Number Segment |
Meaning |
| XC |
Xilinx Commercial |
| KU |
Kintex UltraScale family |
| 095 |
Device density identifier (KU095) |
| -2 |
Speed grade (-2, second-fastest standard grade) |
| FFVB |
Package type: Fine-pitch Flip-chip BGA (FCBGA), B variant |
| 1760 |
Package pin count (1760 pins) |
| I |
Temperature range: Industrial (-40°C to +100°C) |
This industrial-grade (-I suffix) device is rated for extended temperature operation, making it suitable for rugged environments and mission-critical applications.
XCKU095-2FFVB1760I Key Specifications
Core Device Parameters
| Parameter |
Value |
| Manufacturer |
AMD (Xilinx) |
| Part Number |
XCKU095-2FFVB1760I |
| FPGA Family |
Kintex UltraScale |
| Technology Node |
20nm |
| Logic Cells |
1,176,000 |
| Speed Grade |
-2 |
| Supply Voltage (VCCINT) |
0.95V |
| Package |
1760-Pin FCBGA (FFVB1760) |
| Package Body Size |
45mm × 45mm |
| Operating Temp. Range |
–40°C to +100°C (Industrial) |
| Lifecycle Status |
Production |
Logic and Fabric Resources
| Resource |
Quantity |
| System Logic Cells |
1,176,000 |
| CLB LUTs |
537,600 |
| CLB Flip-Flops |
1,075,200 |
| DSP Slices (DSP48E2) |
2,760 |
| Block RAM (36Kb blocks) |
1,080 |
| Total Block RAM Capacity |
38,880 Kb |
| UltraRAM (288Kb blocks) |
0 (KU series) |
I/O and Connectivity
| Feature |
Value |
| Maximum User I/O (Package) |
702 |
| GTH Transceivers |
32 |
| GTY Transceivers |
0 |
| Max GTH Line Rate |
16.3 Gb/s |
| Transceiver Aggregate Bandwidth |
~1,043 Gb/s |
| PCIe Hard Blocks |
2 × Gen3 ×8 |
| 100G Ethernet MACs |
2 |
| 150G Interlaken |
1 |
| Integrated Memory Interface |
DDR4 / DDR3L / LPDDR3 |
Clock Management
| Resource |
Value |
| MMCMs |
20 |
| PLLs |
20 |
| Global Clock Buffers |
576 |
| Max Clock Frequency |
630 MHz |
XCKU095-2FFVB1760I Package and Ordering Information
Package Details
| Parameter |
Value |
| Package Type |
FCBGA (Fine-pitch Flip-Chip Ball Grid Array) |
| Pin Count |
1,760 |
| Body Dimensions |
45mm × 45mm |
| Ball Pitch |
1.0mm |
| Mounting Type |
Surface Mount (SMT) |
| RoHS Compliance |
Yes |
Part Number Variants for KU095 Device
The XCKU095 die is available in multiple speed grades, packages, and temperature ratings. Below is a comparison of the most common variants:
| Part Number |
Speed Grade |
Package |
Pins |
Temp Range |
| XCKU095-2FFVB1760I |
-2 |
FFVB |
1760 |
Industrial |
| XCKU095-2FFVB1760E |
-2 |
FFVB |
1760 |
Extended |
| XCKU095-1FFVB1760I |
-1 |
FFVB |
1760 |
Industrial |
| XCKU095-1FFVB1760C |
-1 |
FFVB |
1760 |
Commercial |
| XCKU095-2FFVA1156I |
-2 |
FFVA |
1156 |
Industrial |
| XCKU095-2FFVA1156E |
-2 |
FFVA |
1156 |
Extended |
| XCKU095-1FFVC1517C |
-1 |
FFVC |
1517 |
Commercial |
Key Features and Technology Highlights
UltraScale Architecture Advantages
The XCKU095-2FFVB1760I is built on Xilinx’s UltraScale architecture, which brings ASIC-level capabilities to programmable logic. Key architectural innovations include:
- ASIC-like clocking: Fine-grained clock gating delivers up to 40% lower dynamic power compared to previous-generation 28nm devices.
- Next-generation DSP48E2 slices: Enhanced DSP slices support wider multipliers for floating-point operations, XOR functions for ECC/CRC, and pre-adder squaring — enabling more computation in fewer resources.
- Advanced Block RAM: UltraScale Block RAM includes hardened memory cascade logic and flexible hard FIFO support, reducing fabric utilization for memory-intensive designs.
- High-performance transceivers: GTH serial transceivers support line rates up to 16.3 Gb/s, enabling 100G Ethernet, PCIe Gen3, Interlaken, and other high-speed protocols directly on chip.
High-Speed Serial Connectivity
The 32 GTH transceivers on the XCKU095 device support a wide range of industry-standard protocols, each with flexible configuration options:
| Protocol |
Supported Standard |
| Ethernet |
100GbE (2× hard MACs) |
| PCIe |
Gen3 ×8 (2× hard blocks) |
| Interlaken |
150G |
| OTN / CPRI / JESD204B |
Supported via GTH |
| Serial Memory (HMC) |
Hybrid Memory Cube |
DDR4 Memory Interface Support
The XCKU095-2FFVB1760I supports high-performance external memory interfaces including DDR4, DDR3L, and LPDDR3, tightly integrated with dedicated I/O circuitry and clock management for maximum throughput and minimal latency.
Target Applications for the XCKU095-2FFVB1760I
The XCKU095-2FFVB1760I is engineered for bandwidth-intensive and compute-heavy workloads. Typical deployment areas include:
Networking and Data Centers
- 100G packet processing and forwarding
- Deep packet inspection (DPI)
- Network line cards and switches
- SmartNIC and FPGA-based acceleration
Wireless and Telecom Infrastructure
- Heterogeneous 4G/5G base station design
- Remote radio head (RRH) digital front-end (DFE)
- CPRI/eCPRI protocol termination
- Massive MIMO signal processing
Video and Broadcast
- 8K4K (8192×4096) video processing
- Real-time video compression and transcoding
- Broadcast signal routing and processing
Defense and Aerospace
- Radar signal processing
- Electronic warfare (EW) systems
- Software-defined radio (SDR)
- Ruggedized industrial control (industrial-grade -I temperature range)
Medical Imaging
- High-resolution CT and MRI reconstruction
- Ultrasound signal processing
- Real-time image analysis pipelines
Development Tools and Design Flow
Xilinx Vivado Design Suite
The XCKU095-2FFVB1760I is fully supported by the Xilinx Vivado Design Suite, Xilinx’s unified design environment for UltraScale and UltraScale+ devices. Vivado provides:
- HDL synthesis and implementation (VHDL / Verilog / SystemVerilog)
- Timing-driven place-and-route
- Power analysis and optimization (Xilinx Power Estimator — XPE)
- Integrated simulation and waveform analysis
- Partial reconfiguration support
Minimum Vivado version for XCKU095: Vivado Design Suite 2015.3 (v1.24 speed spec).
IP Catalog and Reference Designs
The Vivado IP catalog includes pre-verified IP cores for PCIe Gen3, 100G Ethernet, DDR4 memory controllers, JESD204B, and many other interfaces — significantly reducing time-to-market for XCKU095-based designs.
Power Supply Requirements
The XCKU095-2FFVB1760I requires multiple supply rails for proper operation:
| Supply Rail |
Voltage |
Function |
| VCCINT |
0.95V |
Core logic supply |
| VCCAUX |
1.8V |
Auxiliary I/O and PLL supply |
| VCCBRAM |
0.95V |
Block RAM supply |
| VCCO |
1.2V – 3.3V |
I/O bank supply (varies by standard) |
| MGTAVCC |
1.0V |
GTH transceiver analog supply |
| MGTAVTT |
1.2V |
GTH transceiver termination |
Proper power sequencing is required. Xilinx recommends using the XPE tool to estimate rail currents for your specific design.
Comparison: XCKU095 vs. Other Kintex UltraScale Devices
| Feature |
XCKU060 |
XCKU095 |
XCKU115 |
| Logic Cells |
663,360 |
1,176,000 |
1,451,000 |
| DSP Slices |
2,760 |
2,760 |
5,520 |
| Block RAM (Mb) |
32,640 Kb |
38,880 Kb |
75,960 Kb |
| GTH Transceivers |
32 |
32 |
64 |
| Max I/O (B1760 pkg) |
520 |
702 |
702 |
| 100G MACs |
2 |
2 |
4 |
The XCKU095 sits in a performance-optimized mid-range position, offering more I/O density and logic than the XCKU060 while remaining more cost-effective than the XCKU115.
Frequently Asked Questions
What is the XCKU095-2FFVB1760I used for?
The XCKU095-2FFVB1760I is used in high-performance applications including 100G networking, wireless base stations, medical imaging, video processing, defense systems, and FPGA-based compute acceleration.
What is the difference between -1 and -2 speed grades?
The -2 speed grade offers higher performance (faster timing) compared to the -1 speed grade, at the same core voltage (0.95V). Both operate at VCCINT = 0.95V for the XCKU095 device.
What does the “I” suffix mean in XCKU095-2FFVB1760I?
The “I” suffix denotes the Industrial temperature grade, specifying a guaranteed operating range of –40°C to +100°C junction temperature — suitable for demanding environmental conditions.
What software is used to program the XCKU095-2FFVB1760I?
Xilinx Vivado Design Suite (2015.3 or later) is the primary design tool. The Xilinx iMPACT / Vivado Hardware Manager tools are used for device programming via JTAG or configuration memory.
Is the XCKU095-2FFVB1760I RoHS compliant?
Yes, the device is RoHS compliant and is supplied in lead-free packaging.
Summary
The XCKU095-2FFVB1760I is a production-status, industrial-grade Kintex UltraScale FPGA delivering over 1.17 million logic cells, 2,760 DSP slices, 32 GTH transceivers at up to 16.3 Gb/s, and 702 user I/Os in a 1760-pin FCBGA package. Its 20nm UltraScale architecture, combined with hard-IP blocks for PCIe Gen3 and 100G Ethernet, makes it an ideal choice for engineers targeting bandwidth-intensive, compute-heavy designs where price/performance/watt is critical.
For additional product information, datasheets, and pricing, visit our Xilinx FPGA catalog page.
