What Is the XCKU035-L1FBVA900I?

The XCKU035-L1FBVA900I is a high-performance, low-power Field Programmable Gate Array (FPGA) manufactured by AMD Xilinx. It belongs to the Xilinx FPGA Kintex UltraScale family — a mid-range device line that delivers an outstanding balance of performance, power efficiency, and cost-effectiveness. Built on TSMC’s 20nm planar process technology, the XCKU035-L1FBVA900I targets demanding applications in 100G networking, wireless infrastructure, medical imaging, video processing, and data centers.

The part number breaks down as follows: XCKU035 identifies the Kintex UltraScale 035 die, L1 denotes the -1L low-power speed grade, FBVA900 specifies the 900-ball Fine-pitch Ball Grid Array (FCBGA) package, and I indicates industrial temperature rating. This combination makes the XCKU035-L1FBVA900I a compelling choice for engineers who need industrial reliability with reduced static power consumption.

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XCKU035-L1FBVA900I Key Specifications at a Glance

The table below summarizes the most important technical parameters for the XCKU035-L1FBVA900I:

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Understanding the XCKU035-L1FBVA900I Part Number

Decoding the XCKU035-L1FBVA900I part number is essential for procurement and design verification. Each segment carries specific meaning:

The -1L speed grade is a critical differentiator. It operates at either VCCINT = 0.95V (matching standard -1 performance) or VCCINT = 0.90V (lower static power, reduced performance). This dual-voltage capability — sometimes listed as -1LV in Vivado Design Suite when operating at 0.90V — gives designers fine-grained control over the power-performance trade-off.

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XCKU035-L1FBVA900I Logic Resources

Configurable Logic Blocks (CLBs)

The XCKU035-L1FBVA900I uses Xilinx’s UltraScale CLB architecture, which provides an ASIC-like design experience. Each CLB contains 8 six-input LUTs and 16 flip-flops, enabling highly efficient implementation of complex digital logic.

DSP Performance

The XCKU035-L1FBVA900I contains 2,520 DSP48E2 slices, each capable of executing a full multiply-accumulate (MAC) operation in a single clock cycle. This makes it well-suited for signal processing workloads that require high arithmetic throughput, such as radar processing, software-defined radio (SDR), and FIR/IIR filter banks.

Block RAM

With 21.1 Mb of on-chip block RAM organized in 298 dual-port 36Kb tiles, the XCKU035-L1FBVA900I supports wide, high-bandwidth internal memory buffers. Each BRAM tile can be configured as either one 36Kb block or two independent 18Kb blocks, offering flexible memory mapping for packet buffers, FIFOs, and look-up tables.

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XCKU035-L1FBVA900I I/O and Connectivity

High-Performance I/O Banks

The XCKU035-L1FBVA900I provides 468 user I/O pins across multiple high-performance (HP) I/O banks. These banks support a wide range of single-ended and differential I/O standards, enabling seamless interfacing with external memory, FMC modules, and peripheral devices.

GTH Serial Transceivers

The 16 GTH transceivers integrated into the XCKU035-L1FBVA900I operate at up to 16.3 Gb/s per lane. These transceivers support industry-standard protocols out of the box, including PCIe Gen3, 10G/40G/100G Ethernet, CPRI, SRIO, and Interlaken. The transceivers feature built-in equalization, clock data recovery (CDR), and channel bonding for multi-lane applications.

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XCKU035-L1FBVA900I Package and Pinout

900-Pin FCBGA Package (FBVA900)

The XCKU035-L1FBVA900I is housed in a 35mm × 35mm, 900-ball Fine-pitch Chip-Scale BGA (FCBGA) package with a 1.0mm ball pitch. This compact form factor supports high-density PCB designs while maintaining good thermal and signal integrity characteristics. The FBVA900 package is footprint-compatible with other Kintex UltraScale and Virtex UltraScale devices in the same package, enabling scalability within a family without PCB redesign.

PCB Design Considerations for XCKU035-L1FBVA900I

When designing PCBs for the XCKU035-L1FBVA900I, engineers should account for the following:

• Power delivery: Use dedicated power planes for VCCINT (0.95V), VCCAUX (1.8V), and VCCO (variable) supply rails.
• Decoupling capacitors: Place low-ESL ceramic capacitors within 0.5mm of each power ball.
• Thermal management: The device can operate up to 100°C junction temperature; adequate copper pours and thermal vias are recommended.
• Signal integrity: Differential pairs for GTH transceivers require controlled impedance routing (100Ω differential).

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Power Characteristics of the XCKU035-L1FBVA900I

Low-Power -1L Speed Grade

The -1L speed grade is specifically screened for reduced maximum static power compared to standard -1 or -2 devices. When configured to operate at VCCINT = 0.90V (Vivado -1LV mode), the XCKU035-L1FBVA900I achieves its lowest static power floor — ideal for power-sensitive industrial and embedded applications.

Use the Xilinx Power Estimator (XPE) tool and Vivado’s power analysis feature to accurately estimate dynamic power for your specific design before committing to a power supply architecture.

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Supported Protocols and Applications

Target Applications for the XCKU035-L1FBVA900I

The XCKU035-L1FBVA900I excels across a broad spectrum of high-performance embedded applications:

Compatible IP Cores and Vivado Support

The XCKU035-L1FBVA900I is fully supported by the Xilinx Vivado Design Suite, including synthesis, place-and-route, timing closure, and bitstream generation. Verified soft-IP cores available for this device include 100G Ethernet MAC (CMAC), PCIe Gen3 x8 Endpoint, DDR4/LPDDR4 Memory Controllers, and the JESD204B high-speed data converter interface.

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XCKU035-L1FBVA900I vs. Related Kintex UltraScale Variants

The table below compares the XCKU035-L1FBVA900I with closely related variants to help you select the right part:

The XCKU035-L1FBVA900I is footprint-compatible with the XCKU040-L1FBVA900I, allowing a density upgrade without PCB modifications — a key advantage during product scaling.

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Ordering Information

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Frequently Asked Questions About the XCKU035-L1FBVA900I

What does the “L1” mean in XCKU035-L1FBVA900I?

The L1 refers to the -1L low-power speed grade. This speed grade operates at VCCINT = 0.95V with the same timing performance as a standard -1 device, or at VCCINT = 0.90V for reduced static power (listed as -1LV in Vivado tools).

What is the maximum operating temperature for the XCKU035-L1FBVA900I?

The I suffix at the end of the part number indicates an industrial temperature rating, covering a junction temperature range of −40°C to +100°C (Tj). This makes it suitable for harsh industrial, telecommunications, and embedded computing environments.

How many transceivers does the XCKU035-L1FBVA900I have?

The XCKU035-L1FBVA900I has 16 GTH transceivers, each supporting line rates from 0.5 Gb/s up to 16.3 Gb/s. They are grouped into quads and support protocols such as PCIe Gen3, 10G/40G/100G Ethernet, CPRI, and Interlaken.

Is the XCKU035-L1FBVA900I RoHS compliant?

Yes. The XCKU035-L1FBVA900I is fully RoHS compliant and uses lead-free solder balls in its FCBGA package.

What design tools support the XCKU035-L1FBVA900I?

The device is supported by the Xilinx Vivado Design Suite (version 2015.4 or later for production use). AMD also provides free IP cores, reference designs, and simulation models through its IP Catalog and the Kintex UltraScale product documentation portal.

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Summary

The XCKU035-L1FBVA900I is a versatile, industrial-grade Kintex UltraScale FPGA that delivers a compelling mix of logic density, DSP throughput, and serial connectivity in a compact 900-pin FCBGA package. Its -1L low-power speed grade, dual-voltage VCCINT support, 16 GTH transceivers at 16.3 Gb/s, and 2,520 DSP slices make it an excellent choice for engineers designing next-generation networking, wireless, imaging, and embedded processing systems. The industrial temperature range and RoHS compliance further extend its suitability for mission-critical, long-lifecycle deployments.