The XCKU035-2FBVA900E is a mid-range, high-performance Field Programmable Gate Array (FPGA) from AMD Xilinx’s Kintex UltraScale family. Built on a 20 nm process node, it delivers an industry-leading combination of DSP throughput, block RAM capacity, and high-speed serial connectivity — all in a compact 900-pin FCBGA package. Whether you are designing 100G networking equipment, next-generation medical imaging systems, or wireless infrastructure platforms, this device offers the processing power and I/O flexibility your application demands.
For engineers evaluating a broad range of programmable logic solutions, our guide to Xilinx FPGA devices provides an excellent starting point for understanding the full product portfolio.
What Is the XCKU035-2FBVA900E?
The XCKU035-2FBVA900E is part of AMD Xilinx’s Kintex UltraScale product line — a family of FPGAs designed to deliver the best price-per-performance-per-watt ratio available at the 20 nm process node. The part number breaks down as follows:
| Part Number Segment |
Meaning |
| XC |
Xilinx Commercial Device |
| KU |
Kintex UltraScale Family |
| 035 |
Device Size (mid-range density) |
| -2 |
Speed Grade 2 (standard commercial speed) |
| FBVA |
Fine-pitch Ball Grid Array, Flip Chip, FCBGA package type |
| 900 |
900-pin package |
| E |
Commercial temperature grade (0°C to +85°C) |
XCKU035-2FBVA900E Key Specifications
Core Device Attributes
| Parameter |
Value |
| Manufacturer |
AMD (formerly Xilinx) |
| Part Number |
XCKU035-2FBVA900E |
| Family |
Kintex UltraScale |
| Process Node |
20 nm |
| Package Type |
FCBGA (Flip Chip Ball Grid Array) |
| Package Code |
FBVA900 |
| Total Pins |
900 |
| Speed Grade |
-2 (Commercial) |
| Temperature Range |
0°C to +85°C (Commercial Grade) |
| RoHS Compliant |
Yes |
Logic Resources
| Logic Resource |
Count |
| Logic Cells (Macrocells) |
444,343 |
| CLB Logic Blocks |
203,128 |
| DSP Slices (DSP48E2) |
1,700 |
| Maximum DSP Performance |
Up to 661 GMAC/s (Speed Grade -2) |
| CLB LUTs |
~341,040 |
| Flip-Flops |
~682,080 |
The UltraScale CLB architecture places 8 LUTs and 16 flip-flops in every Configurable Logic Block, with SLICEM LUTs configurable as 64-bit distributed RAM or 32-bit shift registers (SRL32).
Memory Resources
| Memory Type |
Capacity |
| Total Block RAM |
19,456 Kbits (~19 Mb) |
| Block RAM Blocks (36Kb each) |
540 |
| Distributed RAM |
Available via LUT-based SLICEM |
| Block RAM Features |
Built-in FIFO logic, ECC support |
Each 36 Kb block RAM can be split into two independent 18 Kb blocks, providing flexible granularity for designs that require smaller memory instances.
I/O and Electrical Characteristics
| Parameter |
Value |
| Total User I/Os |
468 |
| I/O Standard Support |
LVCMOS, LVDS, SSTL, HSTL, and more |
| I/O Supply Voltage |
Up to 3.3V |
| Core Supply Voltage (Min) |
922 mV |
| Core Supply Voltage (Max) |
979 mV |
| Maximum Operating Frequency |
725 MHz |
| Clock Management |
MMCM (Mixed-Mode Clock Manager), PLL |
High-Speed Serial Transceivers
| Transceiver Type |
Count |
Max Line Rate |
| GTH Transceivers |
16 |
Up to 12.5 Gb/s (in FBVA900 package) |
| Aggregate Bandwidth |
~522 Gb/s (full duplex) |
— |
The GTH transceivers in the FBVA900 package support line rates up to 12.5 Gb/s. For applications needing higher transceiver rates (up to 16.3 Gb/s), alternative packages such as the FFVA1156 are available.
Clock Management
| Clock Feature |
Detail |
| CMT Tiles |
MMCM + PLL per tile |
| Clock Regions |
Multiple segmented clock regions |
| Clock Routing |
Dedicated horizontal and vertical clock networks |
| Max Clocks per Region |
24 global clocks, independent regional clocks |
XCKU035-2FBVA900E Package and Physical Details
The FBVA900 package is a Flip Chip Ball Grid Array with a fine-pitch ball arrangement designed for high pin count in a compact board footprint. It is footprint-compatible with other UltraScale devices sharing the same package designator, enabling smooth migration between device densities without PCB redesign.
| Package Attribute |
Value |
| Package Designator |
FBVA900 |
| Total Balls |
900 |
| Package Type |
FCBGA (Flip Chip BGA) |
| Footprint Compatibility |
Compatible with other UltraScale FBVA900 devices |
| Body Size |
Standard 35mm x 35mm |
| PCB Design Guide |
UG583, UltraScale Architecture PCB Design User Guide |
Architecture Highlights: UltraScale Technology
#### Advanced CLB Architecture
The UltraScale CLB is a significant improvement over previous Xilinx 7-Series FPGAs. Each CLB contains a single slice with 8 six-input LUTs and 16 flip-flops — doubling the logic density compared to the prior generation. The enhanced routing architecture reduces congestion in high-utilization designs.
#### High-Performance DSP48E2 Slices
The XCKU035 contains 1,700 DSP48E2 slices, each featuring a 27×18-bit multiplier, a 30-bit pre-adder, and a 96-bit XOR function. These slices are optimized for floating-point calculations, error correction (ECC/CRC), and cascaded DSP chains, making the device ideal for signal-processing-intensive workloads.
#### Block RAM with Integrated FIFO and ECC
All 36 Kb block RAMs include hardened FIFO control logic and optional error correction, eliminating the need for soft logic overhead and improving both density utilization and reliability in memory-intensive pipelines.
#### Segmented Clock Architecture
The clock architecture divides the device into multiple clock regions, each 60 CLBs tall and containing 24 DSP slices, 12 block RAMs, and 4 transceiver channels. This structure delivers repeatable, predictable timing closure across clock domains.
Supported Applications
The XCKU035-2FBVA900E’s combination of logic resources, DSP throughput, high-speed transceivers, and flexible I/O makes it a strong candidate for a wide range of demanding applications.
| Application Area |
Use Case Examples |
| 100G Networking |
Packet processing, line cards, traffic management |
| Wireless Infrastructure |
TD-LTE/5G baseband, DFE, Remote Radio Head (RRH) |
| Medical Imaging |
MRI reconstruction, CT scan processing, ultrasound |
| Video Processing |
4K/8K video encode/decode, broadcast equipment |
| Data Center |
FPGA-accelerated compute, hardware offload |
| Defense and Aerospace |
Signal intelligence, radar processing |
| Industrial Automation |
Real-time control, machine vision |
| Test and Measurement |
High-speed data capture and analysis |
Ordering Information and Part Number Variants
The XCKU035 device is available in multiple packages and speed grades. The table below shows common variants to aid selection.
| Part Number |
Speed Grade |
Package |
Temp Grade |
I/Os |
| XCKU035-2FBVA900E |
-2 |
FBVA900 |
Commercial (0–85°C) |
468 |
| XCKU035-1FBVA900C |
-1 |
FBVA900 |
Commercial |
468 |
| XCKU035-2FBVA900I |
-2 |
FBVA900 |
Industrial (−40–100°C) |
468 |
| XCKU035-1FBVA900I |
-1 |
FBVA900 |
Industrial |
468 |
| XCKU035-2FFVA1156E |
-2 |
FFVA1156 |
Commercial |
Higher I/O |
| XCKU035-2SFVA784E |
-2 |
SFVA784 |
Commercial |
400 |
Design Tools and Development Resources
Designing with the XCKU035-2FBVA900E is fully supported by AMD Xilinx’s Vivado Design Suite, which provides a unified environment for synthesis, implementation, simulation, and hardware debug.
| Resource |
Description |
| Vivado Design Suite |
Primary design entry, synthesis, place & route, timing analysis |
| IP Integrator |
Block design for rapid IP integration |
| Vitis HLS |
High-level synthesis from C/C++/OpenCL |
| DS892 |
Kintex UltraScale FPGA Data Sheet: DC and AC Switching Characteristics |
| DS890 |
UltraScale Architecture and Product Overview |
| UG570 |
UltraScale Architecture Configuration User Guide |
| UG571 |
UltraScale Architecture SelectIO Resources User Guide |
| UG579 |
UltraScale Architecture DSP Slice User Guide |
| UG583 |
UltraScale Architecture PCB Design User Guide |
XCKU035-2FBVA900E vs. Adjacent Family Members
Designers choosing between Kintex UltraScale devices often compare the KU035 against the KU025 (lower density) and KU040 (higher density). The table below summarizes the key differentiators.
| Feature |
XCKU025 |
XCKU035 |
XCKU040 |
| Logic Cells |
~301,440 |
444,343 |
~530,400 |
| DSP Slices |
1,152 |
1,700 |
1,920 |
| Block RAM |
~13 Mb |
~19 Mb |
~21 Mb |
| GTH Transceivers |
12 |
16 |
20 |
| Max I/O (FBVA900) |
— |
468 |
468 |
The KU035 occupies a compelling position in the lineup: it provides substantially more DSP and memory resources than the KU025 while remaining more cost-effective than the KU040 for designs that do not require the highest transceiver count.
Frequently Asked Questions
Q: What is the operating temperature range of the XCKU035-2FBVA900E? A: The “E” suffix designates the commercial temperature grade, which spans 0°C to +85°C. For industrial applications requiring −40°C to +100°C operation, choose the “I” suffix variant such as the XCKU035-2FBVA900I.
Q: What is the maximum GTH transceiver line rate in the FBVA900 package? A: In the FBVA900 package, GTH transceivers support data rates up to 12.5 Gb/s. For the full 16.3 Gb/s GTH rate, consider the FFVA1156 package variant.
Q: Is the XCKU035-2FBVA900E RoHS compliant? A: Yes. This device is fully RoHS compliant and lead-free.
Q: What design software is required for the XCKU035-2FBVA900E? A: AMD Xilinx’s Vivado Design Suite is the required and recommended development environment for all UltraScale family devices.
Q: Can I migrate from an XCKU035 to an XCKU040 without a new PCB? A: Yes, provided both devices are in the same FBVA900 package. UltraScale devices sharing the same package footprint designator are footprint-compatible, enabling density migration without PCB redesign.
Conclusion
The XCKU035-2FBVA900E delivers a compelling combination of 20 nm processing efficiency, 1,700 DSP slices, 468 user I/Os, 16 GTH high-speed transceivers, and rich block RAM resources in an accessible 900-pin FCBGA footprint. It is a proven platform for 100G networking, wireless base stations, high-resolution medical imaging, and data center acceleration workloads. With full support from Vivado’s mature tool ecosystem and extensive AMD Xilinx reference designs, this device provides an efficient and low-risk path from concept to production.
