The XC3S400-5FG320C is a high-performance, cost-optimized Field Programmable Gate Array (FPGA) from the Xilinx Spartan-3 family, now manufactured under the AMD umbrella. Designed for high-volume, cost-sensitive applications, the XC3S400-5FG320C delivers 400K system gates, 8,064 logic cells, and operates at up to 725 MHz — all in a compact 320-pin Fine-pitch Ball Grid Array (FBGA) package. Whether you are an engineer sourcing components for embedded systems, telecommunications, or industrial control, this guide covers everything you need to know about the XC3S400-5FG320C.
What Is the XC3S400-5FG320C?
The XC3S400-5FG320C is part of Xilinx’s Spartan-3 FPGA series, a family engineered to bring programmable logic to high-volume, price-sensitive markets. Built on 90nm process technology and powered by a 1.2V core supply, it builds on the foundation of the earlier Spartan-IIE family by significantly expanding logic resources, internal RAM capacity, I/O count, and overall performance.
The “-5” speed grade in the part number indicates the fastest speed bin in the Spartan-3 lineup, while “FG320” denotes the 320-pin FBGA package, and “C” designates commercial temperature range (0°C to +85°C). For engineers working on Xilinx FPGA designs, the XC3S400-5FG320C offers an ideal balance between logic density, I/O flexibility, and unit cost.
XC3S400-5FG320C Key Specifications
General Product Information
| Parameter |
Value |
| Manufacturer |
AMD (Xilinx) |
| Part Number |
XC3S400-5FG320C |
| Product Family |
Spartan-3 |
| Series |
XC3S400 |
| Package Type |
320-Pin FBGA (Fine-pitch BGA) |
| Package Dimensions |
19mm × 19mm |
| Mounting Type |
Surface Mount |
| RoHS Status |
Not Compliant |
Logic & Performance Specifications
| Parameter |
Value |
| System Gates |
400,000 (400K) |
| Logic Cells |
8,064 |
| CLB Array (Rows × Columns) |
16 × 24 |
| Total CLBs |
384 |
| Slices per CLB |
4 |
| Total Slices |
3,584 |
| Flip-Flops |
7,168 |
| Maximum Frequency |
725 MHz |
| Process Technology |
90nm |
| Core Supply Voltage (VCCINT) |
1.2V |
Memory Resources
| Memory Type |
Capacity |
| Total Block RAM |
288 Kbits (16 × 18Kb blocks) |
| Distributed RAM |
55 Kbits |
| Total RAM Bits |
368,640 |
I/O and Interface Specifications
| Parameter |
Value |
| Total Package Pins |
320 |
| Maximum User I/O |
264 |
| I/O Banks |
8 |
| Differential I/O Pairs |
Up to 132 |
| Single-Ended Standards |
18 (including LVCMOS, LVTTL, SSTL, HSTL) |
| Differential Standards |
8 (including LVDS, RSDS, BLVDS, LVPECL) |
| Max Data Rate per I/O |
622+ Mb/s |
| Signal Swing Range |
1.14V to 3.465V |
| DDR/DDR2 SDRAM Support |
Up to 333 Mb/s |
| Digitally Controlled Impedance |
Yes |
Digital Clock Management (DCM)
| Parameter |
Value |
| Number of DCM Blocks |
4 |
| DCM Functions |
Clock frequency synthesis, phase shifting, deskewing |
| Clock Networks |
8 global clock networks |
Multiplier Resources
| Parameter |
Value |
| Dedicated 18×18 Multipliers |
16 |
XC3S400-5FG320C Part Number Decoder
Understanding the part number helps you select the right variant for your design:
| Segment |
Meaning |
| XC |
Xilinx Commercial IC |
| 3S |
Spartan-3 family |
| 400 |
400K logic gate density |
| -5 |
Speed grade 5 (fastest in family) |
| FG |
Fine-pitch Ball Grid Array (FBGA) package |
| 320 |
320 total package pins |
| C |
Commercial temperature range (0°C to +85°C) |
XC3S400-5FG320C Architecture Overview
Configurable Logic Blocks (CLBs)
The XC3S400-5FG320C organizes its logic into Configurable Logic Blocks. Each CLB contains four slices, and each slice holds two 4-input Look-Up Tables (LUTs), two flip-flops, wide fast multiplexers, and fast look-ahead carry logic. The LUTs can be optionally used as 16-bit shift registers or 16-bit distributed RAM, giving designers maximum flexibility per logic element.
SelectRAM Hierarchical Memory
Memory in the XC3S400-5FG320C follows a two-tier hierarchy. Block SelectRAM provides 16 dedicated 18 Kbit RAM blocks, each configurable as true dual-port or single-port memory in aspect ratios from 16K×1 to 512×36. Distributed SelectRAM allows logic LUTs to operate as 16×1-bit single-port or 16×1-bit dual-port RAM, enabling lightweight local data storage with minimal routing delay.
Digital Clock Management (DCM)
The four on-chip DCM blocks provide precise clock control including frequency synthesis, phase shifting (0° to 360° in fine steps), and input clock deskewing. This makes the XC3S400-5FG320C particularly well-suited to synchronous designs requiring multiple clock domains or tight timing closure.
SelectIO Interface Technology
The device supports 18 single-ended and 8 differential I/O standards with Digitally Controlled Impedance (DCI), eliminating the need for external termination resistors on high-speed signals. Double Data Rate (DDR) support allows interfacing with DDR and DDR2 SDRAM at up to 333 Mb/s.
Electrical Characteristics
| Parameter |
Value |
| Core Supply Voltage (VCCINT) |
1.2V |
| I/O Supply Voltage (VCCO) |
1.2V – 3.3V (bank-configurable) |
| Auxiliary Supply Voltage (VCCAUX) |
2.5V |
| Operating Temperature (Commercial) |
0°C to +85°C |
| ESD Protection |
HBM Class 2 |
Supported I/O Standards
Single-Ended Standards
| Standard |
Description |
| LVCMOS 3.3V / 2.5V / 1.8V / 1.5V |
General-purpose CMOS logic levels |
| LVTTL |
3.3V TTL compatible |
| SSTL 2 / SSTL 18 |
For DDR/DDR2 SDRAM interfaces |
| HSTL Class I / II |
High-speed transceiver logic |
| PCI / PCI-X |
Peripheral Component Interconnect |
Differential Standards
| Standard |
Description |
| LVDS |
Low-Voltage Differential Signaling |
| RSDS |
Reduced Swing Differential Signaling |
| BLVDS |
Bus LVDS |
| LVPECL |
Low-Voltage Positive Emitter-Coupled Logic |
| ULVDS |
Ultra Low-Voltage Differential Signaling |
XC3S400-5FG320C vs. Other Spartan-3 Variants
| Part Number |
Gates |
Logic Cells |
Package Pins |
Speed Grade |
Temp Range |
| XC3S400-4FG320C |
400K |
8,064 |
320 |
-4 |
Commercial |
| XC3S400-5FG320C |
400K |
8,064 |
320 |
-5 (Fastest) |
Commercial |
| XC3S400-4FG320I |
400K |
8,064 |
320 |
-4 |
Industrial |
| XC3S1000-5FG320C |
1M |
17,280 |
320 |
-5 |
Commercial |
| XC3S200-5PQ208C |
200K |
4,320 |
208 |
-5 |
Commercial |
The XC3S400-5FG320C occupies the sweet spot of the Spartan-3 lineup for 320-pin designs — offering maximum gate density in this footprint combined with the fastest -5 speed grade for timing-critical applications.
Typical Applications for XC3S400-5FG320C
The XC3S400-5FG320C is widely used across many industries thanks to its combination of logic density, I/O flexibility, and low power consumption:
- Embedded Systems — Custom logic controllers, bus bridges, and co-processors alongside microcontrollers or microprocessors
- Communications & Networking — Protocol converters, packet processing, and interface bridges in broadband access equipment
- Industrial Automation — Motor drive controllers, PLC logic expansions, and sensor data aggregation
- Consumer Electronics — Set-top boxes, digital television decoders, and home networking equipment
- Digital Signal Processing — Custom FIR/IIR filter implementations using dedicated 18×18 multiplier blocks
- Test & Measurement — Data acquisition front-ends and configurable signal routing matrices
- Automotive Electronics — Infotainment system logic and gateway ECU controllers
Configuration and Programming
The XC3S400-5FG320C supports multiple configuration modes:
| Mode |
Description |
| Master Serial |
FPGA reads bitstream from serial flash |
| Slave Serial |
Bitstream loaded by external processor |
| Master Parallel (SelectMAP) |
Fast parallel configuration bus |
| Slave Parallel (SelectMAP) |
Parallel load under external control |
| JTAG (IEEE 1149.1 / 1532) |
Boundary scan and in-system programming |
The device supports configuration from SPI flash, BPI flash, and Platform Flash NOR memory. Configuration bitstream size for the XC3S400 is approximately 1,699,267 bits (~212 KB).
Development Tools and Design Flow
Designing with the XC3S400-5FG320C is supported by both legacy and current AMD-Xilinx toolchains:
| Tool |
Purpose |
| Xilinx ISE Design Suite 14.7 |
Legacy HDL synthesis, implementation, and bitstream generation |
| Vivado Design Suite |
Modern design environment (supports legacy device simulation) |
| ModelSim / QuestaSim |
RTL and gate-level simulation |
| ChipScope Pro |
In-system logic analysis and debugging |
| iMPACT |
Device configuration and boundary-scan testing |
HDL support includes VHDL, Verilog, and SystemVerilog. IP cores for common protocols such as UART, SPI, I2C, and DDR memory controllers are available through Xilinx IP catalog and open-source repositories.
Ordering and Availability
| Field |
Detail |
| DigiKey Part Number |
122-1888-ND |
| Manufacturer Part Number |
XC3S400-5FG320C |
| Manufacturer |
AMD (Xilinx) |
| Standard Package Quantity |
Tray |
| Moisture Sensitivity Level |
MSL 3 (168 hours floor life) |
| Minimum Order Quantity |
1 |
Note: The XC3S400-5FG320C is a mature product that may have limited availability through standard distribution channels. Always verify stock and lead times with your authorized distributor.
Frequently Asked Questions (FAQ)
Q: What is the difference between XC3S400-5FG320C and XC3S400-4FG320C? The only difference is the speed grade. The “-5” variant is the fastest available, offering lower propagation delays and support for higher clock frequencies compared to the “-4” grade. Choose “-5” for timing-critical designs and “-4” where cost optimization is the priority.
Q: Is the XC3S400-5FG320C RoHS compliant? No. This particular part number (ending in “C” without a lead-free suffix) is not RoHS compliant. If your application requires RoHS compliance, look for the equivalent part with a lead-free package designation from Xilinx or consider a Spartan-3E or Spartan-6 replacement.
Q: Can I use Vivado to design for the XC3S400-5FG320C? The XC3S400-5FG320C is not directly supported as an implementation target in Vivado. The recommended tool is Xilinx ISE Design Suite 14.7, which remains available as a free download from AMD and provides full support for all Spartan-3 devices.
Q: What is the maximum user I/O count in the 320-pin package? The XC3S400-5FG320C supports up to 264 user I/O pins in the FG320 package, organized across 8 I/O banks.
Q: What replacement or equivalent exists for the XC3S400-5FG320C? For new designs, consider migrating to the Spartan-6 XC6SLX25 or XC6SLX45, which offer significantly more logic resources, lower power, and a more modern toolchain while maintaining I/O compatibility in equivalent BGA packages.
Summary
The XC3S400-5FG320C is a proven, capable FPGA delivering 400K system gates, 8,064 logic cells, and 264 user I/Os in a surface-mount 320-pin FBGA package. Its -5 speed grade, 4 DCM blocks, 16 dedicated multipliers, and broad I/O standard support make it well-suited to a wide range of embedded, communications, industrial, and consumer applications. While it is a mature device, it remains widely used in existing designs and available through specialized distributors for maintenance and repair applications.
