The XC2S200-6FGG1170C is a high-performance field-programmable gate array (FPGA) from Xilinx’s Spartan-II family. It delivers 200,000 system gates, 5,292 logic cells, and a blazing-fast -6 speed grade — all housed in a 1170-ball Fine-Pitch BGA (FGG1170) Pb-free package. Whether you are designing embedded control systems, communications hardware, or digital signal processing applications, this device offers powerful programmable logic at a cost-effective price point.
If you are sourcing programmable logic solutions, explore the full range of Xilinx FPGA products available for your next design project.
What Is the XC2S200-6FGG1170C?
The XC2S200-6FGG1170C is a member of Xilinx’s Spartan-II FPGA product line, fabricated on a 0.18μm process technology and operating at a 2.5V core supply voltage. It belongs to the largest device in the Spartan-II family — the XC2S200 — and is configured with:
- Speed grade: -6 (the fastest available, commercial temperature range only)
- Package: FGG1170 — a 1170-ball Fine-Pitch Ball Grid Array (FBGA), Pb-free (RoHS-compliant “G” designation)
- Temperature range: Commercial (0°C to +85°C), denoted by the “C” suffix
The Spartan-II family was designed to serve as a cost-optimized alternative to mask-programmed ASICs. Unlike ASICs, the XC2S200-6FGG1170C can be reprogrammed in the field without hardware replacement — offering significant savings in development time and non-recurring engineering (NRE) costs.
XC2S200-6FGG1170C Key Specifications
Core Logic Resources
| Parameter |
XC2S200 Value |
| System Gates (Logic + RAM) |
200,000 |
| Logic Cells |
5,292 |
| CLB Array |
28 × 42 |
| Total CLBs |
1,176 |
| Maximum User I/O Pins |
284 |
| Distributed RAM (bits) |
75,264 |
| Block RAM (bits) |
56K |
Device Identification & Ordering Information
| Parameter |
Value |
| Part Number |
XC2S200-6FGG1170C |
| Manufacturer |
Xilinx (now AMD) |
| FPGA Family |
Spartan-II |
| Speed Grade |
-6 (fastest) |
| Package Type |
FGG1170 (1170-ball Fine-Pitch BGA, Pb-free) |
| Temperature Grade |
Commercial (0°C to +85°C) |
| RoHS Compliance |
Yes (Pb-free “G” package) |
| Process Technology |
0.18μm |
| Core Supply Voltage |
2.5V |
| Max System Frequency |
Up to 200 MHz |
Electrical Characteristics
| Electrical Parameter |
Value |
| Core (VCC) Supply Voltage |
2.5V |
| I/O Supply Voltage (VCCO) |
1.5V, 1.8V, 2.5V, or 3.3V |
| Input Voltage (High) |
2.0V (min, 3.3V LVTTL) |
| Input Voltage (Low) |
0.8V (max, 3.3V LVTTL) |
| Max System Clock Frequency |
200 MHz |
| Max Distributed RAM Frequency |
263 MHz |
XC2S200-6FGG1170C Architecture Overview
Configurable Logic Blocks (CLBs)
The XC2S200 contains 1,176 CLBs arranged in a 28×42 array. Each CLB includes four logic cells organized into two slices, and every logic cell contains:
- A 4-input Look-Up Table (LUT)
- A flip-flop (D-type with clock enable and synchronous set/reset)
- Carry logic for arithmetic operations
- Wide function multiplexers
This architecture allows designers to implement complex combinatorial and sequential logic efficiently within a single device.
Block RAM
The XC2S200 includes 56K bits of dedicated block RAM, organized as two columns of dual-port synchronous RAM blocks on opposite sides of the die. Each block RAM can be independently configured in various aspect ratios, supporting designs that require large on-chip data storage such as FIFOs, lookup tables, and frame buffers.
Distributed RAM
With 75,264 bits of distributed RAM, logic cells can be configured as read/write memory. This distributed RAM operates at up to 263 MHz and is ideal for shift registers and smaller data buffers spread throughout the logic fabric.
Delay-Locked Loops (DLLs)
The XC2S200 features four Delay-Locked Loops (DLLs), one placed at each corner of the die. These DLLs eliminate clock distribution delays, enable frequency synthesis, and support phase shifting — making it straightforward to implement reliable, high-frequency synchronous designs.
Input/Output Blocks (IOBs)
The device supports up to 284 user-configurable I/O pins, with each IOB supporting multiple programmable I/O standards including:
- LVTTL
- LVCMOS (1.5V, 1.8V, 2.5V, 3.3V)
- PCI (3.3V, 32/64-bit, 33/66 MHz)
- SSTL2 and SSTL3
- GTL and GTL+
- AGP
FGG1170 Package Details
Package Specifications
| Package Parameter |
Value |
| Package Type |
Fine-Pitch Ball Grid Array (FBGA) |
| Ball Count |
1,170 |
| Lead-Free (Pb-free) |
Yes (“G” in part number) |
| Package Code |
FGG1170 |
The FGG1170 package is the largest available for the XC2S200, providing the highest pin count and maximum routing flexibility for complex PCB designs. The fine-pitch BGA footprint requires careful PCB design considerations, including controlled-impedance routing and via-in-pad or dog-bone fanout strategies.
Package Comparison for XC2S200
| Package |
Pins |
Type |
Pb-Free |
| PQ208 |
208 |
PQFP |
No |
| PQG208 |
208 |
PQFP |
Yes |
| FG256 |
256 |
FBGA |
No |
| FGG256 |
256 |
FBGA |
Yes |
| FG456 |
456 |
FBGA |
No |
| FGG456 |
456 |
FBGA |
Yes |
| FGG1170 |
1,170 |
FBGA |
Yes |
Note: The FGG1170 package is exclusively Pb-free. It provides the most I/O flexibility for the XC2S200 die.
Speed Grade -6: What It Means
The -6 speed grade designates the fastest performance tier in the Spartan-II family. A higher number corresponds to faster propagation delays and shorter setup/hold times. Key points about the -6 speed grade:
- It is available only in the commercial temperature range (0°C to +85°C)
- It is ideal for applications requiring maximum clock frequencies
- Typical system performance is supported at up to 200 MHz
- Distributed RAM performance reaches up to 263 MHz
Speed Grade Comparison
| Speed Grade |
Temperature Range |
Relative Performance |
| -5 |
Commercial & Industrial |
Standard |
| -6 |
Commercial only |
Fastest |
Ordering Information Breakdown
Understanding the XC2S200-6FGG1170C part number is straightforward once you decode each segment:
| Part Number Segment |
Meaning |
| XC |
Xilinx FPGA product |
| 2S |
Spartan-II family |
| 200 |
200,000 system gates |
| -6 |
Speed grade (fastest) |
| FGG |
Fine-Pitch BGA, Pb-free |
| 1170 |
1,170 ball count |
| C |
Commercial temperature (0°C to +85°C) |
Applications for the XC2S200-6FGG1170C
The XC2S200-6FGG1170C is well-suited for a wide range of applications where programmable logic, high I/O counts, and reprogrammability are required:
#### Communications & Networking
- Line-rate packet processing
- Protocol bridging and conversion
- Wireless baseband processing
#### Industrial & Embedded Control
- Motor drive controllers
- Real-time sensor data acquisition
- Programmable machine vision systems
#### Consumer Electronics
- Set-top box logic and control
- Printer controllers and connected peripherals
- Display drivers and timing controllers
#### Defense & Aerospace (Commercial Grade)
- Signal processing front-ends
- Test and measurement instrumentation
#### Computing & Peripherals
- PCI bus interface logic
- Co-processing accelerators
- Memory controllers
Spartan-II Family Comparison
The XC2S200 sits at the top of the Spartan-II device family. The table below compares all members:
| Device |
Logic Cells |
System Gates |
CLB Array |
Max User I/O |
Dist. RAM (bits) |
Block RAM (bits) |
| XC2S15 |
432 |
15,000 |
8×12 |
86 |
6,144 |
16K |
| XC2S30 |
972 |
30,000 |
12×18 |
92 |
13,824 |
24K |
| XC2S50 |
1,728 |
50,000 |
16×24 |
176 |
24,576 |
32K |
| XC2S100 |
2,700 |
100,000 |
20×30 |
176 |
38,400 |
40K |
| XC2S150 |
3,888 |
150,000 |
24×36 |
260 |
55,296 |
48K |
| XC2S200 |
5,292 |
200,000 |
28×42 |
284 |
75,264 |
56K |
Design Tools & Programming
Supported Design Software
The XC2S200-6FGG1170C is supported by Xilinx ISE Design Suite (legacy toolchain). While the newer Vivado Design Suite does not support Spartan-II devices, ISE provides a complete end-to-end flow including:
- Synthesis (XST)
- Place & Route
- Timing Analysis
- JTAG-based configuration via iMPACT
Configuration Modes
The XC2S200 supports multiple configuration modes:
| Configuration Mode |
Description |
| Master Serial |
Loads bitstream from serial PROM |
| Slave Serial |
Controlled by an external microprocessor |
| Master Parallel (SelectMAP) |
Fast parallel byte-wide configuration |
| Slave Parallel (SelectMAP) |
Processor-driven parallel configuration |
| JTAG (Boundary Scan) |
IEEE 1149.1-compliant, via JTAG header |
Recommended Configuration PROMs
- Xilinx XC17V16 / XC17V32 serial PROMs
- Platform Flash (XCF) series for production designs
Why Choose the XC2S200-6FGG1170C?
- Maximum gate density in the Spartan-II family with 200K system gates
- Highest speed grade (-6) for demanding, high-frequency designs
- 1170-ball Pb-free BGA package for maximum I/O availability
- Reprogrammability eliminates ASIC NRE costs and design lock-in
- Mature, proven silicon with extensive field deployment history
- Multi-standard I/O support simplifies integration with diverse system components
- Four on-chip DLLs enable clean, jitter-minimized clock distribution
Frequently Asked Questions
What is the difference between XC2S200-5 and XC2S200-6?
The -6 speed grade is faster than the -5 speed grade. The -6 grade achieves lower propagation delays and supports higher operating frequencies. However, the -6 speed grade is only available in the commercial temperature range (0°C to +85°C), while the -5 is available in both commercial and industrial (−40°C to +100°C) ranges.
Is the FGG1170 package lead-free?
Yes. The “G” in “FGG1170” indicates a Pb-free (lead-free) package, meeting RoHS compliance requirements for environmentally responsible manufacturing.
What software do I need to program the XC2S200-6FGG1170C?
The recommended toolchain is Xilinx ISE Design Suite. The Vivado Design Suite does not support Spartan-II devices. Programming is performed via JTAG using Xilinx iMPACT or through a serial/parallel PROM configuration setup.
What is the core supply voltage for the XC2S200?
The XC2S200 operates with a 2.5V core supply voltage. The I/O supply (VCCO) is flexible and can be set to 1.5V, 1.8V, 2.5V, or 3.3V per I/O bank.
Can the XC2S200-6FGG1170C be used in industrial temperature applications?
No. The “C” suffix indicates commercial temperature range (0°C to +85°C). For industrial temperature operation (−40°C to +100°C), choose a part with the “I” suffix, such as the XC2S200-5FGG1170I (if available).
Summary
The XC2S200-6FGG1170C combines Xilinx’s proven Spartan-II architecture with the fastest available speed grade and a large 1170-ball Pb-free BGA package. With 200,000 system gates, 5,292 logic cells, 284 I/O pins, four DLLs, and 56K bits of block RAM, it delivers the performance and flexibility required for demanding digital design applications. Its field-reprogrammability, broad I/O standard support, and cost-effective positioning make it a compelling choice for engineers seeking a proven programmable logic solution.
