Meta Description: The XC2S200-6FGG1136C is a high-performance Xilinx Spartan-II FPGA with 200K system gates, 1,136-pin FBGA package, and -6 speed grade. Explore full specs, features, pinout, and applications in this complete guide.
What Is the XC2S200-6FGG1136C?
The XC2S200-6FGG1136C is a field-programmable gate array (FPGA) manufactured by Xilinx, part of the Spartan-II 2.5V family. This device delivers 200,000 system gates in a 1,136-ball Fine-Pitch Ball Grid Array (FBGA) package with a -6 speed grade — the fastest commercially available speed grade in the Spartan-II lineup. The “C” suffix confirms it operates in the commercial temperature range (0°C to +85°C), while the “GG” in the package code indicates a Pb-free (RoHS-compliant) package option.
Whether you are working on embedded control systems, telecommunications hardware, industrial automation, or consumer electronics, the XC2S200-6FGG1136C offers a compelling balance of logic density, I/O flexibility, and cost-effectiveness. For a broader look at the full Xilinx product lineup, visit the Xilinx FPGA resource page.
XC2S200-6FGG1136C Key Specifications at a Glance
Quick-Reference Specification Table
| Parameter |
Value |
| Part Number |
XC2S200-6FGG1136C |
| Manufacturer |
Xilinx (AMD) |
| FPGA Family |
Spartan-II |
| System Gates |
200,000 |
| Logic Cells |
5,292 |
| CLB Array |
28 × 42 |
| Total CLBs |
1,176 |
| Maximum User I/O |
284 |
| Distributed RAM (bits) |
75,264 |
| Block RAM (bits) |
56K (56,000) |
| Supply Voltage |
2.5V |
| Process Technology |
0.18 µm |
| Speed Grade |
-6 (fastest commercial) |
| Maximum System Clock |
263 MHz |
| Package Type |
FGG1136 (Fine-Pitch BGA) |
| Number of Pins |
1,136 |
| Package Lead Finish |
Pb-Free (RoHS compliant) |
| Operating Temperature |
0°C to +85°C (Commercial) |
Decoding the XC2S200-6FGG1136C Part Number
Understanding the part number helps engineers confirm they are ordering the exact variant they need.
Part Number Breakdown Table
| Segment |
Meaning |
| XC |
Xilinx Commercial FPGA |
| 2S |
Spartan-II Family |
| 200 |
200,000 System Gates |
| -6 |
Speed Grade (fastest = -6) |
| FGG |
Fine-Pitch Ball Grid Array, Pb-Free |
| 1136 |
1,136 Total Pins/Balls |
| C |
Commercial Temperature (0°C to +85°C) |
The “-6” speed grade is exclusively available in the commercial temperature range, making the XC2S200-6FGG1136C the optimal choice for high-speed designs that do not require industrial or automotive temperature ratings.
XC2S200-6FGG1136C Architecture and Internal Structure
Configurable Logic Blocks (CLBs)
The XC2S200-6FGG1136C contains 1,176 Configurable Logic Blocks arranged in a 28-column by 42-row matrix. Each CLB consists of two logic cells (slices), and each slice contains two 4-input Look-Up Tables (LUTs) and two flip-flops. This architecture enables efficient implementation of both combinatorial and registered logic, including arithmetic functions, state machines, and data path elements.
Distributed RAM
The device provides 75,264 bits of distributed RAM derived from the LUTs within the CLBs. This memory is ideal for small, fast storage buffers, shift registers, and FIFOs that sit close to the logic consuming them, minimizing routing delays.
Block RAM
In addition to distributed memory, the XC2S200-6FGG1136C includes 56,000 bits (56K) of dedicated Block RAM. The block RAM columns are positioned on opposite sides of the die between the CLB array and the IOB columns. Block RAM supports true dual-port access and is ideal for larger memory structures such as lookup tables, packet buffers, and embedded data storage.
Input/Output Blocks (IOBs) and I/O Standards
The XC2S200-6FGG1136C supports up to 284 user I/O pins (excluding the four global clock/user input pins). Each IOB supports a wide range of programmable I/O standards, giving engineers flexibility in interfacing with external components.
Supported I/O Standards
| I/O Standard |
Description |
| LVTTL |
Low-Voltage TTL (3.3V) |
| LVCMOS2 |
Low-Voltage CMOS (2.5V) |
| PCI |
3.3V PCI Bus |
| GTL / GTL+ |
Gunning Transceiver Logic |
| HSTL Class I/II |
High-Speed Transceiver Logic |
| SSTL2 Class I/II |
Stub Series Terminated Logic (2.5V) |
| SSTL3 Class I/II |
Stub Series Terminated Logic (3.3V) |
| CTT |
Center Tap Terminated |
| AGP |
Accelerated Graphics Port |
Delay-Locked Loops (DLLs)
The XC2S200-6FGG1136C features four on-chip Delay-Locked Loops (DLLs), one placed at each corner of the die. These DLLs allow designers to eliminate clock distribution skew, perform clock multiplication and division, and shift clock phase relationships — all without external components.
XC2S200-6FGG1136C vs. Other Spartan-II Devices
The table below compares the XC2S200 against other members of the Spartan-II family to help engineers select the right device for their logic density requirements.
Spartan-II Family Comparison Table
| Device |
Logic Cells |
System Gates |
CLB Array |
Max User I/O |
Distributed RAM |
Block RAM |
| XC2S15 |
432 |
15,000 |
8 × 12 |
86 |
6,144 bits |
16K bits |
| XC2S30 |
972 |
30,000 |
12 × 18 |
92 |
13,824 bits |
24K bits |
| XC2S50 |
1,728 |
50,000 |
16 × 24 |
176 |
24,576 bits |
32K bits |
| XC2S100 |
2,700 |
100,000 |
20 × 30 |
176 |
38,400 bits |
40K bits |
| XC2S150 |
3,888 |
150,000 |
24 × 36 |
260 |
55,296 bits |
48K bits |
| XC2S200 |
5,292 |
200,000 |
28 × 42 |
284 |
75,264 bits |
56K bits |
As the table shows, the XC2S200 is the highest-density member of the Spartan-II family. It provides the most logic cells, the largest CLB array, the highest user I/O count, and the greatest memory resources of any device in the family.
FGG1136 Package Details
Package Physical Characteristics
| Package Parameter |
Value |
| Package Type |
Fine-Pitch Ball Grid Array (FBGA) |
| Total Ball Count |
1,136 |
| Lead Finish |
Pb-Free (RoHS compliant, “GG” designation) |
| Package Standard |
FGG1136 |
| Ball Pitch |
Fine-Pitch (0.8 mm) |
The FGG1136 package is the largest available package for the XC2S200, providing the full complement of 284 user I/O pins. This makes it the best choice when maximum I/O connectivity is required. The Pb-free (lead-free) package construction satisfies RoHS environmental compliance requirements for global markets.
Performance Characteristics of the XC2S200-6FGG1136C
Speed Grade -6: The Fastest Spartan-II
The -6 speed grade is the highest-performance speed grade in the Spartan-II family. It supports a maximum system clock frequency of 263 MHz and delivers the shortest propagation delays across CLBs, routing resources, and IOBs. This makes the XC2S200-6FGG1136C the ideal option when a design is constrained by timing requirements rather than power or cost.
Timing Performance Summary
| Timing Parameter |
-6 Speed Grade |
| Maximum Clock Frequency |
263 MHz |
| Speed Grade Rank |
Fastest (Commercial only) |
| Temperature Availability |
Commercial (0°C to +85°C) only |
| LUT Propagation Delay |
Minimum (fastest grade) |
| IOB Setup Time |
Minimum (fastest grade) |
Important: The -6 speed grade is not available in industrial (-40°C to +100°C) or extended temperature ranges. If your application requires operation beyond 0°C to +85°C, consider the -5 or -4 speed grades.
Configuration and Programming
Configuration Modes
The XC2S200-6FGG1136C supports multiple configuration modes, giving engineers flexibility in how the device loads its bitstream at power-up.
| Configuration Mode |
Description |
| Master Serial |
FPGA drives a serial PROM (e.g., XCF family) |
| Slave Serial |
External controller drives configuration data |
| Master Parallel (SelectMAP) |
8-bit parallel bus, FPGA in master mode |
| Slave Parallel (SelectMAP) |
8-bit parallel bus, FPGA in slave mode |
| JTAG (Boundary Scan) |
IEEE 1149.1 compliant, via TAP controller |
Configuration Memory
The Spartan-II family uses SRAM-based configuration cells, meaning the design is volatile and must be reloaded from external non-volatile memory (such as a Xilinx Platform Flash PROM) on every power cycle. This SRAM architecture is what enables the device’s full in-field reprogrammability.
Boundary Scan (JTAG) Support
The XC2S200-6FGG1136C fully supports IEEE 1149.1 boundary scan, enabling in-system testing, device identification, and board-level interconnect testing. The JTAG interface can also be used for device configuration and programming.
Electrical Characteristics
Absolute Maximum Ratings
| Parameter |
Value |
| Core Supply Voltage (VCCINT) |
2.5V ± 5% |
| I/O Supply Voltage (VCCO) |
Up to 3.6V |
| Input Voltage Range |
–0.5V to VCCO + 0.5V |
| Storage Temperature |
–65°C to +150°C |
| Operating Temperature (Commercial) |
0°C to +85°C |
Power Supply Requirements
The Spartan-II architecture operates on a 2.5V core supply (VCCINT). The I/O banks (VCCO) can accept a different supply voltage depending on the I/O standard in use, ranging from 1.5V (for HSTL) up to 3.3V (for LVTTL and PCI).
Key Features and Benefits of the XC2S200-6FGG1136C
- 200,000 system gates — the highest density in the Spartan-II family
- 5,292 logic cells with 1,176 CLBs for complex logic implementation
- 284 user I/O pins in the full FGG1136 package
- -6 speed grade for maximum timing performance up to 263 MHz
- Four on-chip DLLs for zero-skew clock distribution and clock management
- 75,264 bits of distributed RAM for fast, embedded data storage
- 56K bits of block RAM for larger memory buffers
- Multiple I/O standards including LVTTL, PCI, HSTL, SSTL2, and more
- JTAG boundary scan support for in-system test and programming
- RoHS-compliant Pb-free package (FGG designation)
- SRAM-based reprogrammability — full in-field design updates without hardware replacement
- Cost-effective ASIC alternative — eliminates NRE (non-recurring engineering) costs
Typical Applications of the XC2S200-6FGG1136C
The XC2S200-6FGG1136C is well-suited for a broad range of applications due to its combination of high logic density, rich I/O support, and maximum speed grade performance.
Application Areas
| Application Domain |
Use Case Examples |
| Telecommunications |
Protocol bridges, framing engines, line cards |
| Industrial Automation |
Motor controllers, PLCs, sensor interfaces |
| Data Acquisition |
ADC/DAC interfaces, signal processing |
| Embedded Systems |
Soft-core processor (MicroBlaze), custom SoC |
| Consumer Electronics |
Display controllers, video processing |
| Test & Measurement |
Pattern generation, data capture, BERT |
| Automotive (Non-Safety-Critical) |
Dashboard controllers, infotainment (commercial temp) |
| Military/Aerospace (Prototype) |
Early-stage design validation (commercial temp version) |
Design Tools and Software Support
The XC2S200-6FGG1136C is fully supported by the Xilinx ISE Design Suite, which includes:
- XST (Xilinx Synthesis Technology) — HDL synthesis for VHDL and Verilog
- ISE Simulator (ISim) — Functional and timing simulation
- PACE / PlanAhead — Pinout assignment and floor-planning
- iMPACT — Device programming and configuration file generation
- ChipScope Pro — In-system signal monitoring and debugging
Note: The Spartan-II family is supported through ISE Design Suite. The newer Vivado Design Suite does not support Spartan-II devices. Always use ISE 14.7 (the final ISE release) for Spartan-II designs.
Ordering Information and Part Number Variants
XC2S200 Available Packages and Variants
| Part Number |
Package |
Pins |
Speed Grade |
Temperature |
Pb-Free |
| XC2S200-6FGG1136C |
FGG1136 (FBGA) |
1,136 |
-6 |
Commercial |
Yes |
| XC2S200-5FGG1136C |
FGG1136 (FBGA) |
1,136 |
-5 |
Commercial |
Yes |
| XC2S200-4FGG1136C |
FGG1136 (FBGA) |
1,136 |
-4 |
Commercial |
Yes |
| XC2S200-6FG456C |
FG456 (FBGA) |
456 |
-6 |
Commercial |
No |
| XC2S200-5FG456C |
FG456 (FBGA) |
456 |
-5 |
Commercial |
No |
| XC2S200-5FGG456C |
FGG456 (FBGA) |
456 |
-5 |
Commercial |
Yes |
| XC2S200-5FG256C |
FG256 (FBGA) |
256 |
-5 |
Commercial |
No |
| XC2S200-6PQ208C |
PQ208 (PQFP) |
208 |
-6 |
Commercial |
No |
When choosing between variants, note that the FGG1136 package provides the maximum I/O count of 284 pins, while smaller packages (FG256, PQ208) expose fewer I/O at lower cost and PCB footprint.
XC2S200-6FGG1136C vs. Competitive FPGAs
How Does It Compare?
| Feature |
XC2S200-6FGG1136C (Xilinx) |
Altera Cyclone EP1C12 |
Lattice EC6 |
| System Gates |
200,000 |
~200,000 |
~200,000 |
| Logic Elements |
5,292 LCs |
12,060 LEs |
~6,000 LUTs |
| Max User I/O |
284 |
249 |
270 |
| Block RAM |
56K bits |
239,616 bits |
55K bits |
| Supply Voltage |
2.5V |
1.5V |
1.2V |
| Max Clock |
263 MHz |
~200 MHz |
~200 MHz |
| Package Options |
FBGA, PQFP |
BGA, TQFP |
BGA, TQFP |
The XC2S200-6FGG1136C holds a competitive edge in maximum clock frequency, I/O count, and ecosystem support through Xilinx ISE. For designs already using Xilinx tooling, it offers a seamless development path.
Frequently Asked Questions (FAQ)
What does the “GG” in FGG1136 mean?
The double “G” in the package designation (FGG vs. FG) indicates a Pb-free, RoHS-compliant package. This is distinct from the standard (non-Pb-free) FG456 package.
Is the XC2S200-6FGG1136C still in production?
The Spartan-II family has reached end-of-life. However, the XC2S200-6FGG1136C remains widely available through authorized distributors and component brokers for legacy system maintenance and replacement.
What is the difference between -6, -5, and -4 speed grades?
The -6 speed grade offers the shortest timing delays and highest maximum clock frequency (263 MHz). The -5 and -4 grades have progressively longer delays but may be more cost-effective or easier to source. The -6 grade is available only in the commercial temperature range (0°C to +85°C).
Can I replace an XC2S200-6FGG1136C with a newer Xilinx device?
Yes, but it requires a design migration. Xilinx recommends migrating Spartan-II designs to the Spartan-6 (XC6S) or Artix-7 (XC7A) families. Spartan-6 and Artix-7 offer significantly more resources, lower power, higher performance, and continued tool support in Vivado.
What configuration PROM should I use with the XC2S200-6FGG1136C?
Xilinx Platform Flash PROMs such as the XCF02S (2 Mbit) or XCF04S (4 Mbit) are commonly used for Spartan-II configuration. The XC2S200 requires approximately 1.67 Mbit of configuration data.
Summary: Why Choose the XC2S200-6FGG1136C?
The XC2S200-6FGG1136C stands as the top-of-the-line option in the Spartan-II family. It combines the family’s highest logic density, the maximum user I/O count, the fastest available speed grade, and a Pb-free large-pin-count package. For engineers maintaining legacy designs, sourcing replacement parts, or designing cost-sensitive systems that are well-served by Spartan-II capability, the XC2S200-6FGG1136C remains a reliable and proven choice.
Its full architecture — encompassing 5,292 logic cells, four DLLs, 75,264 bits of distributed RAM, 56K bits of block RAM, and 284 user I/Os — gives designers everything needed to implement complex digital systems without the NRE costs and long lead times of custom ASICs.
