The XC2S200-6FGG1035C is a high-density, 2.5V field-programmable gate array (FPGA) from Xilinx’s Spartan-II family. Designed for cost-sensitive, high-volume applications, it delivers 200,000 system gates and 5,292 logic cells in a 1035-ball Fine Pitch BGA (FBGG) package. Whether you’re replacing an ASIC, shortening your design cycle, or building a scalable embedded system, the XC2S200-6FGG1035C offers an exceptional combination of density, speed, and programmability. For a broader overview of the full product line, visit Xilinx FPGA.

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What Is the XC2S200-6FGG1035C?

The XC2S200-6FGG1035C belongs to the Xilinx Spartan-II FPGA family, a series of 0.18µm process-based, SRAM-based programmable logic devices. This part number decodes as follows:

• XC2S200 – Spartan-II device with 200K system gates
• -6 – Speed grade 6 (fastest commercially available grade for this family)
• FGG – Fine Pitch Ball Grid Array, Pb-free (green) package
• 1035 – 1035 total pins
• C – Commercial temperature range (0°C to +85°C)

This device is widely used in telecommunications, data processing, industrial control, and embedded applications where reconfigurability and cost-effectiveness matter most.

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XC2S200-6FGG1035C Key Specifications

General Device Parameters

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Logic and Memory Resources

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Performance and Timing Characteristics

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XC2S200-6FGG1035C Package Details

1035-Ball FBGG Package Overview

The 1035-pin FBGG package is one of the largest available in the Spartan-II lineup, making it the ideal choice for designs that need the maximum number of I/O pins — up to 284 user I/Os — while benefiting from a compact BGA footprint.

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Spartan-II Family Comparison Table

Use this table to understand how the XC2S200 compares to other members of the Spartan-II FPGA family:

The XC2S200 is the highest-density device in the Spartan-II family, offering the most logic cells, the most CLBs, the most I/Os, and the largest memory resources.

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Key Features of the XC2S200-6FGG1035C Spartan-II FPGA

Advanced Logic Architecture

The Spartan-II logic fabric is built around Configurable Logic Blocks (CLBs), each containing look-up tables (LUTs), flip-flops, and carry logic. This architecture supports efficient implementation of both combinatorial and sequential logic. The 28×42 CLB array in the XC2S200 provides 1,176 CLBs for maximum design flexibility.

Four Delay-Locked Loops (DLLs)

The XC2S200-6FGG1035C includes four on-chip Delay-Locked Loops, one at each corner of the die. The DLLs allow designers to:

• Eliminate clock distribution delay
• Synthesize new clock frequencies
• Phase-shift and duty-cycle correct clock signals
• Achieve synchronous clock distribution across the entire device

Dual Block RAM Columns

Two columns of block RAM run along opposite sides of the die, providing 56K bits of fast, synchronous on-chip memory. Block RAM supports true dual-port access, making it ideal for FIFOs, data buffers, and lookup tables.

Flexible Input/Output Blocks (IOBs)

The XC2S200-6FGG1035C supports multiple I/O standards through its configurable IOBs:

• LVTTL, LVCMOS (2.5V, 3.3V)
• PCI (3.3V, 33 MHz and 66 MHz)
• GTL, GTL+
• HSTL (Class I, II, III, IV)
• SSTL2 and SSTL3 (Class I and II)
• AGP-2X

Boundary Scan (JTAG) Support

Full IEEE 1149.1 JTAG boundary scan is implemented, enabling in-system testing and debugging without physical test probes.

Configuration Options

The XC2S200-6FGG1035C supports multiple configuration modes:

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XC2S200-6FGG1035C Ordering Information Decoded

Understanding the Xilinx part number helps you select the exact variant for your application:

Note: The “-6” speed grade is exclusively available in the Commercial temperature range (0°C to +85°C). For industrial temperature range (-40°C to +85°C), speed grades -4 and -5 are available.

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Typical Applications for the XC2S200-6FGG1035C

The XC2S200-6FGG1035C is well-suited for a wide range of applications, including:

• Telecommunications – Line cards, protocol bridging, data framing
• Networking – Packet processing, interface bridging, switching logic
• Industrial Automation – Motor control, sensor interfaces, PLC replacement
• Embedded Systems – Custom co-processors, bus interfaces, glue logic
• Consumer Electronics – Video processing pipelines, display controllers
• Prototyping & ASIC Replacement – Rapid prototyping of ASIC designs

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Why Choose the XC2S200-6FGG1035C Over a Mask-Programmed ASIC?

The XC2S200-6FGG1035C enables engineers to avoid the initial cost, lengthy development cycles, and inherent risk of ASICs while still achieving the high integration and I/O density required for complex designs.

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XC2S200-6FGG1035C vs. Comparable FPGA Devices

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Frequently Asked Questions (FAQ)

What does the “G” in FGG mean on the XC2S200-6FGG1035C?

The double “G” in FGG indicates a Pb-free (lead-free) package. Xilinx introduced this notation to distinguish RoHS-compliant, green packaging from legacy leaded variants. Single “G” (e.g., FG) indicates a standard leaded package.

Is the XC2S200-6FGG1035C still in production?

The Spartan-II family has been designated as Not Recommended for New Designs (NRND). However, it remains available through authorized distributors for maintenance of existing designs. For new designs, Xilinx/AMD recommends migrating to the Spartan-6 or Artix-7 FPGA families.

What software tools are used with the XC2S200-6FGG1035C?

The XC2S200-6FGG1035C is supported by Xilinx ISE Design Suite (version 14.x is the final supported release for Spartan-II). Xilinx Vivado does not support Spartan-II devices.

What is the core supply voltage for the XC2S200-6FGG1035C?

The device operates at a core supply voltage of 2.5V (VCCINT). The I/O voltage (VCCO) can range from 1.5V to 3.3V depending on the I/O standard selected.

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Summary: XC2S200-6FGG1035C at a Glance

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The XC2S200-6FGG1035C is a proven solution for high-I/O, cost-sensitive programmable logic designs. With its 200K gate capacity, 284 user I/Os, 56K bits of block RAM, and the fastest -6 commercial speed grade, it delivers the performance and flexibility engineers need. Explore the full range of available devices at Xilinx FPGA.