Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.
Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.
Notes: For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.
J-STD-075 Guide: PSL Classification for Passive Components & Assembly Process Limits
The transition to lead-free soldering exposed a problem that many of us in PCB assembly hadn’t fully anticipated: passive components failing during reflow. I remember debugging a production line where film capacitors were cracking after the third reflow pass, and tantalum capacitors were showing increased leakage current. The issue wasn’t moisture sensitivity. It was thermal process sensitivity, and that’s exactly what J-STD-075 was designed to address.
If you work with passive components like capacitors, inductors, fuses, or crystals, understanding J-STD-075 is essential. This standard extends the moisture sensitivity concepts from J-STD-020 to cover all the ways passive components can be damaged during assembly processes, not just by absorbed moisture.
J-STD-075, officially titled “Classification of Passive and Solid State Devices for Assembly Processes,” is a joint standard developed by ECIA (Electronic Components Industry Association), IPC, and JEDEC. The standard establishes worst-case solder assembly process conditions and provides a classification system called Process Sensitivity Level (PSL) for components that cannot withstand standard assembly processes.
The fundamental purpose of J-STD-075 is to identify components with thermal, cleaning, or other process limitations before they cause assembly failures. While J-STD-020 focuses specifically on moisture sensitivity for IC packages, J-STD-075 expands this concept to address the unique sensitivities of passive components and provides a unified labeling system.
J-STD-075 Standard Overview
Attribute
Specification
Full Title
Classification of Passive and Solid State Devices for Assembly Processes
Publisher
ECIA / IPC / JEDEC (Joint Standard)
Current Revision
J-STD-075A (May 2018)
Original Release
August 2008
Page Count
~20 pages
Supersedes
IPC-9503
Scope
Passive components, solid-state devices
J-STD-075 Revision History
Revision
Release Date
Key Changes
J-STD-075
August 2008
Original release, focused on non-IC components
J-STD-075A
May 2018
Extended scope to solid-state devices, updated title
The 2018 revision (J-STD-075A) changed the title from “Classification of Non-IC Electronic Components” to “Classification of Passive and Solid State Devices” to reflect the expanded scope that now includes solid-state components with process sensitivities.
Why Passive Components Need Their Own Standard
Passive components present unique challenges that J-STD-020 wasn’t designed to address:
Passive Component Vulnerability Factors
Factor
Issue
Affected Components
No encapsulation
Direct thermal exposure
Film capacitors, inductors
Open construction
Cleaning fluid penetration
Chokes, wire-wound components
Thermal mass
Rapid heating damage
Large electrolytic capacitors
Material limitations
Lower temperature tolerance
Aluminum, polymer capacitors
Mechanical stress
Thermal shock cracking
Ceramic capacitors
Unlike plastic-encapsulated ICs that have a protective mold compound, many passive components expose internal materials directly to the soldering environment. This means thermal damage can occur even without moisture involvement.
Common Passive Component Failures from Assembly
Component Type
Failure Mode
Root Cause
Film Capacitors
Parameter drift, cracking
Excessive peak temperature
Aluminum Electrolytics
Electrolyte degradation
High temperature exposure
Tantalum Capacitors
Increased leakage current
Thermal stress
Ceramic Capacitors
Cracking, flex cracks
Thermal shock
Inductors
Core saturation change
Excessive temperature
Crystals/Oscillators
Frequency shift
Thermal damage
Fuses
Premature opening
Reflow temperature
Understanding Process Sensitivity Level (PSL)
The core of J-STD-075 is the Process Sensitivity Level (PSL) classification system. Unlike MSL which is a single number (1-6), PSL uses a three-character code that conveys more detailed information about component sensitivities.
PSL Rating Structure
Character Position
Meaning
Values
1st Character
Solder process type
W = Wave, R = Reflow
2nd Character
Thermal sensitivity level
0-9 (0 = meets base conditions)
3rd Character
Other process sensitivities
Letter code (G, C, V, X, etc.)
PSL Second Character (Thermal Sensitivity)
Value
Wave Solder Meaning
Reflow Meaning
0
Meets base wave conditions
Meets base reflow conditions
1
1 wave pass only
1 reflow cycle only
2
Reduced peak temp required
2 reflow cycles only
3-9
Further restrictions
Further restrictions
PSL Third Character (Other Sensitivities)
Code
Meaning
Typical Components
G
No additional sensitivities
Standard components
C
Cleaning sensitive
Open construction parts
V
Vacuum pick-up sensitive
Fragile packages
X
X-ray sensitive
Some sensors
M
Multiple sensitivities
Combination of above
PSL Rating Examples
PSL Code
Interpretation
R0G
Reflow: Meets base conditions (3 cycles), no other sensitivities
J-STD-075 defines base solder process conditions that components must withstand to be classified as PSL x0x (second character = 0). Components that cannot meet these conditions require PSL classification and labeling.
Base Wave Solder Process Conditions
Parameter
Requirement
Number of Passes
2 passes
Preheat Temperature
Per profile
Solder Pot Temperature
260°C ±5°C (Pb-free)
Contact Time
3-5 seconds per pass
Cooling Rate
Natural convection
Base Reflow Solder Process Conditions
The base reflow conditions align with J-STD-020 requirements:
Parameter
Small Components
Large Components
Number of Reflows
3 cycles
3 cycles
Peak Temperature (Tc)
260°C
260°C
Time Above Liquidus
60-150 seconds
60-150 seconds
Ramp Rate
3°C/second max
3°C/second max
Preheat
150-200°C, 60-120 sec
150-200°C, 60-120 sec
Component Size Classification for Reflow
Package Volume
Classification Temperature
< 350 mm³
260°C
350-2000 mm³
260°C
> 2000 mm³
250°C
J-STD-075 vs J-STD-020: Understanding the Relationship
These standards are complementary, not competing:
Aspect
J-STD-020
J-STD-075
Focus
Moisture sensitivity
Process sensitivity
Component Scope
ICs (semiconductor packages)
Passives, solid-state devices
Classification
MSL 1-6
PSL (3-character code)
Primary Concern
Moisture-induced damage
Thermal/process damage
Handling Standard
J-STD-033
J-STD-033 (for MSL portion)
Test Basis
Moisture soak + reflow
Soldering process evaluation
How the Standards Work Together
The J-STD-075 evaluation process follows this sequence:
Step
Action
Standard Reference
1
Evaluate against base solder conditions
J-STD-075
2
If passes, PSL 2nd character = 0
J-STD-075
3
If fails, determine PSL rating
J-STD-075
4
Use determined conditions for MSL testing
J-STD-020
5
Label and pack per MSL requirements
J-STD-033
This means a component’s PSL rating affects how its MSL is determined. If a component can only withstand 2 reflow cycles instead of 3, the MSL classification must use that 2-cycle condition.
Cleaning Sensitivity Classification
J-STD-075 addresses cleaning sensitivity, which is particularly important for passive components with open constructions.
Components at Risk for Cleaning Damage
Component Type
Cleaning Risk
Failure Mode
Common-mode Chokes
High
Adhesive degradation, corrosion
Pressed-powder Inductors
High
Material erosion, shorts
Naked Film Capacitors
High
Moisture ingress, parameter drift
Wire-in-air Fuses
High
Corrosion, premature failure
Open-frame Transformers
Medium
Insulation damage
Unsealed Potentiometers
Medium
Contact contamination
Cleaning Sensitivity Considerations
Factor
Impact
High-pressure spray
Mechanical damage to delicate structures
Immersion cleaning
Fluid trapped in open constructions
Alkaline agents
Polymer degradation, metal corrosion
Ultrasonic cleaning
Resonance damage to crystals, ceramics
Drying temperature
Secondary thermal stress
J-STD-075 encourages PSL labeling for cleaning sensitivities (3rd character = C) but does not define specific test protocols due to the wide variation in cleaning processes used across the industry.
Other Process Sensitivities
Beyond thermal and cleaning sensitivities, J-STD-075 addresses additional process concerns:
Vacuum Pick-up Sensitivity
Concern
Affected Components
Mitigation
Surface damage
Thin-wall electrolytics
Reduced vacuum force
Seal integrity
Vented capacitors
Modified nozzle design
Mechanical stress
Fragile ceramics
Gentle placement settings
X-Ray Sensitivity
Concern
Affected Components
Consideration
Cumulative dose
Some sensors, memories
Limit inspection passes
Permanent damage
Radiation-sensitive devices
Alternative inspection methods
PSL Labeling Requirements
When a supplier determines that a component is process sensitive (PSL 2nd character > 0), J-STD-075 requires specific labeling.
MSL (Moisture Sensitivity Level) from J-STD-020 specifically addresses damage caused by absorbed moisture vaporizing during reflow, which primarily affects plastic-encapsulated ICs. PSL (Process Sensitivity Level) from J-STD-075 addresses broader process sensitivities including thermal limitations, cleaning sensitivity, and other assembly process concerns. A component can have both an MSL rating and a PSL rating. For example, a polymer tantalum capacitor might be MSL 3 (moisture sensitive, 7-day floor life) and PSL R4G (limited to specific reflow conditions). Both ratings must be considered when planning assembly processes.
Do all passive components need PSL classification?
Classification requirements differ by component type. Per J-STD-075, PSL classification is required for passive devices. Solid-state devices that have already been classified per J-STD-020 and can withstand the J-STD-020 thermal profile are not required to be classified per J-STD-075 for thermal limitations. However, any solid-state device with a history of thermal limitations or sensitivity to cleaning or other processes is strongly recommended to be classified for those process limitations. In practice, many passive component manufacturers don’t provide PSL ratings, which is why assembly engineers often need to establish their own process limits through qualification testing.
Why don’t most passive components have PSL labels?
Despite J-STD-075 being available since 2008, industry adoption remains limited. Many passive component manufacturers are unfamiliar with the standard or consider the testing and labeling costs prohibitive for commodity components. There’s also limited customer demand since many assemblers aren’t aware that PSL classification exists. This creates a gap where thermally sensitive components enter assembly processes without proper documentation. High-reliability industries (aerospace, medical, automotive) are more likely to require PSL information from their suppliers, but consumer electronics often operates without this data.
How many reflow cycles can passive components typically withstand?
It varies significantly by component type. Ceramic capacitors (MLCCs) and ferrite inductors generally withstand 3+ reflows without issue. Standard tantalum capacitors typically handle 3 reflows. Polymer tantalum and conductive polymer aluminum capacitors may be limited to 2 reflows or have specific temperature restrictions. Film capacitors, especially those with low-melting-point dielectrics like polypropylene, may require reduced peak temperatures or fewer cycles. When PSL information isn’t available, conservative practice is to limit passive components to 2 reflow cycles and verify critical parameters after assembly qualification.
Does J-STD-075 cover rework processes?
No, J-STD-075 explicitly states that it does not establish rework simulation conditions. The standard focuses on initial assembly processes. However, it does highlight commonly used alternate solder assembly processes for attaching replacement devices, and recommends that suppliers determine if their devices are sensitive to the temperature values and durations of these alternate processes. For rework guidance, assemblers should consult component datasheets, manufacturer application notes, and IPC-7711/7721 (Rework, Modification and Repair of Electronic Assemblies) while considering the cumulative thermal exposure the component has already experienced.
Conclusion
J-STD-075 fills a critical gap in electronics assembly standards by addressing the process sensitivities of passive components and solid-state devices that J-STD-020 wasn’t designed to cover. The PSL classification system provides a standardized way to communicate thermal limitations, cleaning sensitivities, and other process constraints that can affect component reliability.
The key points to remember:
For Design Engineers: Consider PSL requirements when selecting passive components. A film capacitor with PSL R3C may limit your assembly process options and complicate rework procedures.
For Process Engineers: When PSL information isn’t available from suppliers, establish your own process limits through qualification testing. Document the thermal profiles your passive components experience during assembly.
For Quality Engineers: Request PSL information from passive component suppliers, especially for critical applications. The lack of industry-wide adoption doesn’t mean the information isn’t available. Some suppliers do characterize their products per J-STD-075.
For Procurement: Include J-STD-075 PSL requirements in component specifications for high-reliability applications. This drives supplier awareness and ensures you receive the process sensitivity information you need.
As lead-free soldering with higher reflow temperatures becomes even more prevalent, and as components continue to miniaturize with thinner dielectrics and more sensitive materials, the importance of understanding process sensitivity only grows. J-STD-075 provides the framework for this understanding, even if industry adoption hasn’t yet matched the standard’s value.
The standard works best alongside J-STD-020 for MSL requirements and J-STD-033 for handling and packing. Together, these documents provide comprehensive protection against assembly-induced damage for all surface mount components, not just semiconductor packages.
Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.
Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.
Notes: For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.