ITEQ Laminate Stack-Up Design Guide for High-Speed PCBs

In the high-stakes world of 112G PAM4 and 5G millimeter-wave design, the PCB stack-up is no longer just a mechanical carrier; it is a complex, frequency-dependent component. As signal rise times shrink to the picosecond range, the interaction between the copper, the resin, and the glass weave determines whether your prototype will pass compliance or end up as an expensive paperweight.

For hardware engineers, ITEQ has become a strategic partner in this transition. By providing a clear roadmap from standard High-Tg materials to “Extreme Low Loss” (ELL) substrates, ITEQ allows for a balanced approach to ITEQ stack-up design that harmonizes signal integrity with manufacturing yield. This guide provides a deep-dive, engineer-to-engineer look at architecting high-speed stack-ups using the ITEQ portfolio.

1. Defining the Loss Hierarchy: Selecting the Core Material

The first step in any high-speed stack-up is matching the material’s dissipation factor ($Df$) to the project’s insertion loss budget. A common mistake is over-specifying the material for a short-reach channel or under-specifying for a long-reach backplane.

Table 1: ITEQ High-Speed Material Performance Matrix

Material Class	Typical ITEQ Grade	Dk @ 10GHz	Df @ 10GHz	Target Application
Mid-Loss / High-Tg	IT-180A	4.10	0.016	PCIe Gen 3, Control Planes
Low-Loss	IT-150DA	3.65	0.006	10G Ethernet, 5G Sub-6
Very Low-Loss	IT-968	3.66	0.005	100G/400G, PCIe Gen 5
Ultra Low-Loss	IT-988G	3.63	0.0029	400G/800G, 112G PAM4
Extreme Low-Loss	IT-988G SE	3.24	0.0014	800G+, AI Infrastructure

From a design perspective, IT-180A is the reliability workhorse for layers that don’t carry high-speed signals. However, for 112G PAM4 interfaces, the move to IT-988G SE is mandatory to keep the eye diagram open over traces exceeding 5 inches.

2. Architecting the Hybrid Stack-Up: Performance vs. Cost

A homogeneous stack-up (using the same high-end material for all layers) is often cost-prohibitive. The “ITEQ hybrid stack-up” strategy involves using premium Ultra-Low Loss (ULL) materials for signal layers and cost-effective High-Tg materials for power and ground planes.

Hybrid Design Rules

CTE Matching: Ensure the Z-axis Coefficient of Thermal Expansion (CTE) of both materials is similar to prevent delamination during reflow. ITEQ’s high-speed resins are specifically formulated to be “FR-4 process compatible” to facilitate these hybrids.

Lamination Pressure: High-speed resins like IT-988G often require specific lamination cycles. When designing a hybrid, the “lowest common denominator” for temperature and pressure must be managed by the fabricator to ensure the resin flows and fills the copper gaps perfectly.

Symmetry: Maintain physical symmetry to prevent “bow and twist.” If you use a premium core on Layer 3, use the same core (or a thermally matched one) on the corresponding bottom layer.

3. Managing the “Silent Killers”: Glass Weave and Copper Profile

In an ITEQ stack-up design targeting 28GHz (the Nyquist point for 56G PAM4), the resin is only half the story. The physical texture of the copper and the “knuckles” of the glass weave become dominant loss factors.

The Glass Weave Effect (Skew)

Standard glass cloth has bundles of yarns with resin-rich gaps in between. If one trace of a differential pair sits over a glass bundle and the other over a gap, they see different Dielectric Constants ($Dk$). This causes intra-pair skew, which destroys signal phase relationships.

Engineering Best Practice: Always specify Spread Glass (e.g., styles 1067, 1078, or 3313) for high-speed layers. These “square weave” styles flatten the glass, creating a homogenous dielectric environment that minimizes skew.

Copper Surface Roughness (Skin Effect)

As frequency increases, current is pushed to the outer perimeter of the copper (the skin effect). If the copper surface is rough (like standard RTF), the signal effectively “travels a longer path,” increasing resistance and loss.

Copper Type	Rz Roughness (Typical)	ITEQ Recommendation
Standard RTF	$> 5.0 \mu m$	Avoid for 10Gbps+
VLP (Very Low Profile)	$2.0 – 3.0 \mu m$	10G to 28G NRZ
HVLP / VLP2	$\leq 1.5 \mu m$	56G / 112G PAM4

4. Controlled Impedance and Resin Content Management

The impedance of your traces ($50\Omega$ single-ended or $100\Omega$ differential) depends heavily on the Resin Content (RC%) of the prepreg. ITEQ provides multiple glass styles and resin contents for every material grade.

The “Pressed Thickness” Factor

When the PCB is laminated, the prepreg resin flows to fill the areas between copper traces on the core. This reduces the final thickness of the insulating layer.

Calculate Copper Density: Provide your fabricator with the percentage of copper remaining on each layer.

Resin Filling Calculation: A 1oz copper layer is roughly $35 \mu m$ thick. If the layer is 50% etched, the prepreg must provide enough “extra” resin to fill that $17.5 \mu m$ gap without starving the dielectric.

Impedance Verification: Use ITEQ’s official online stack-up tool or Polar SI9000 to verify your trace widths against the “pressed thickness” rather than the “nominal thickness” of the prepreg.

5. Critical Resources for ITEQ Stack-Up Design

ITEQ Official Online Database: The primary source for frequency-dependent Dk/Df values and specific RC% thickness data.

IPC-2141 / IPC-2251: Industry standards for controlled impedance and high-speed design.

ITEQ Procurement & Support: For real-time material availability and factory stack-up consulting, visit ITEQ PCB resource hubs.

Signal Integrity Software: Import ITEQ material libraries into Ansys HFSS or Keysight ADS for full-channel simulations.

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Frequently Asked Questions (FAQs)

1. Is ITEQ IT-180A suitable for high-speed signals?

IT-180A is a standard High-Tg FR-4. While it is excellent for power and ground planes, its $Df$ of 0.016 is too high for signals above 10Gbps over any significant distance. For high-speed lanes, use IT-968 or IT-988G.

2. What is the benefit of a “Halogen-Free” stack-up?

Beyond environmental compliance, ITEQ’s halogen-free materials (like IT-170G or IT-988G SE) often exhibit lower moisture absorption and higher decomposition temperatures ($Td$), which improves long-term reliability in harsh environments.

3. Why do I need to worry about “Pressed Thickness”?

Impedance is highly sensitive to the distance between the trace and its reference plane. If you use the nominal prepreg thickness instead of the pressed thickness (which accounts for resin flow), your impedance will be off by 5–10%, potentially failing SI margins.

4. How do I mitigate Intra-Pair Skew in 112G PAM4?

Use a combination of Spread Glass laminates and Trace Rotation (routing the signals at a 10-degree angle to the glass weave). This ensures that both traces of a differential pair see the same average amount of glass and resin.

5. What is the difference between IT-988G and IT-988G SE?

The “SE” (Special Edition) variant uses an optimized resin system and Low-Dk glass to push the $Df$ even lower (to 0.0014), making it the preferred choice for 800G switches and AI infrastructure where the loss budget is extremely tight.

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Conclusion: Architecting for 2026 and Beyond

Success in ITEQ stack-up design is about finding the “sweet spot” where electrical performance, thermal reliability, and cost intersect. By understanding the ITEQ hierarchy—from the mechanical stability of IT-180A to the electrical transparency of IT-988G SE—and by managing the secondary effects of copper roughness and glass weave, you can build a 112G-capable board that is as manufacturable as it is fast.