Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.
Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.
Notes: For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.
If you’ve ever dealt with excessive voiding under a QFN thermal pad or struggled with floating components during reflow, you know the frustration that bottom termination components can cause. These leadless packages offer fantastic benefits—smaller footprint, better thermal performance, lower inductance—but they come with unique assembly challenges that traditional SMT guidelines don’t adequately address. That’s exactly why IPC-7093 exists.
In this guide, I’ll break down everything IPC-7093 covers, from land pattern calculations to stencil design strategies that actually reduce voiding. After years of troubleshooting QFN assembly issues, I can tell you this standard is essential reading for anyone working with leadless packages.
What Is IPC-7093?
IPC-7093, officially titled “Design and Assembly Process Implementation for Bottom Termination Components (BTCs),” is an IPC standard that provides comprehensive guidance for designing and assembling leadless surface mount packages. Originally released in March 2011 with Revision A published in October 2020, IPC-7093 addresses the unique challenges posed by components whose electrical connections consist entirely of metallized terminals on the bottom surface.
The standard covers all bottom termination package families including QFN (Quad Flat No-lead), DFN (Dual Flat No-lead), SON (Small Outline No-lead), LGA (Land Grid Array), MLP (Micro Leadframe Package), and MLF (Micro Lead Frame). Despite their different names—often reflecting marketing distinctions rather than technical differences—these packages share common design and assembly requirements that IPC-7093 addresses comprehensively.
IPC-7093 targets physical designers, process engineers, reliability engineers, and managers responsible for design, assembly, inspection, and repair of printed board assemblies containing BTCs. The standard provides practical guidance rather than just theoretical requirements, making it valuable for real-world production environments.
Why IPC-7093 Matters for Modern Electronics
The QFN packaging market alone was valued at approximately $575 million to $1.2 billion in 2024, with projections showing growth to $1.2-2.5 billion by 2031-2033 at CAGRs ranging from 8% to 13%. This growth reflects the fundamental value that bottom termination components deliver across virtually every electronics sector.
The BTC Advantage
Bottom termination components have become dominant in many applications for compelling reasons. Their leadless design provides a near-chip-scale footprint—a 32-pin QFN can reduce board area by 84% compared to a traditional 28-pin PLCC. The exposed die attach pad (DAP) on the bottom surface provides excellent thermal dissipation directly to the PCB. Short connection paths reduce parasitic inductance, making BTCs ideal for RF and high-speed applications. Over 60% of wireless chipsets now use QFN packaging due to these superior electrical characteristics.
The Assembly Challenge
However, BTCs present unique assembly challenges that IPC-7093 specifically addresses. The lack of visible solder fillets makes inspection difficult—you cannot see whether a proper solder joint has formed. The large thermal pad is prone to voiding during reflow, potentially compromising both thermal performance and reliability. Low standoff height makes flux residue cleaning problematic. Component floating during reflow can cause opens on perimeter terminals. These challenges require specific design and process strategies that IPC-7093 provides.
BTC Package Types Covered in IPC-7093
IPC-7093 addresses all major bottom termination package families:
Package Type
Full Name
Typical Application
Key Characteristics
QFN
Quad Flat No-lead
RF, power management, microcontrollers
4-sided perimeter pads + thermal pad
DFN
Dual Flat No-lead
Analog ICs, sensors, small discretes
2-sided perimeter pads + thermal pad
SON
Small Outline No-lead
Power MOSFETs, voltage regulators
Similar to DFN, various sizes
LGA
Land Grid Array
High pin-count ICs, processors
Array pad pattern, no thermal pad
MLP/MLF
Micro Leadframe Package
General-purpose ICs
Leadframe-based construction
Despite different nomenclature, these packages share common assembly requirements. The critical distinction IPC-7093 makes is between packages with exposed thermal pads (most QFN/DFN/SON) and those with only perimeter or array connections (LGA). Each configuration requires different design approaches.
Land Pattern Design Guidelines in IPC-7093
Proper land pattern design is fundamental to successful BTC assembly. IPC-7093 provides detailed guidance on calculating pad dimensions that accommodate component tolerances while enabling reliable solder joints.
Tolerance Calculation Method
IPC-7093 recommends converting supplier tolerances from ±X.XX format to Maximum Material Condition (MMC) and Least Material Condition (LMC) values. Since three tolerance sets are involved—overall package dimensions, terminal length, and terminal width—the standard recommends RMS (root-mean-square) calculations rather than worst-case stacking. This realistic approach prevents overly conservative designs that waste board space.
Perimeter Pad Design
For perimeter terminals, IPC-7093 provides specific land protrusion guidelines:
Dimension
Description
Typical Value
JT (Toe)
Outward extension beyond terminal
0.0 to 0.05 mm
JH (Heel)
Inward extension toward package center
0.0 to 0.05 mm
JS (Side)
Lateral extension beyond terminal width
0.0 to 0.05 mm
The minimal protrusion values reflect the reality that BTC terminals are embedded in mold compound on three sides—only the bottom surface contacts solder. Unlike leaded packages where toe and heel fillets provide mechanical strength, BTC joints rely primarily on the bottom surface contact area.
SMD vs NSMD Pad Definition
IPC-7093 addresses the choice between Solder Mask Defined (SMD) and Non-Solder Mask Defined (NSMD) pad configurations:
Approach
Advantages
Disadvantages
NSMD
Better solder joint reliability (solder bonds to pad top and sides), tighter dimensional control
Potential for solder bridging
SMD
Reduced bridging risk, controlled solder volume
Slightly lower reliability, less precise mask registration
For most applications, NSMD pads are preferred for perimeter terminals due to superior reliability. SMD pads may be appropriate when bridging risk is high or when specific solder volume control is required.
Thermal Pad Design and Voiding Prevention
The exposed thermal pad is simultaneously the greatest benefit and greatest challenge of QFN/DFN packages. IPC-7093 provides extensive guidance on thermal pad design to optimize thermal performance while minimizing assembly defects.
The Voiding Problem
Voiding under thermal pads is the most common QFN assembly defect. Industry data shows voiding frequently exceeds 25% of the pad area, with some assemblies showing over 50% void coverage. Voids form when flux volatiles become trapped under the component during reflow, unable to escape through the low standoff gap.
While there are no universal industry criteria for acceptable voiding in BTC thermal pads (unlike BGAs where IPC standards specify limits), many automotive and high-reliability applications require less than 25% voiding for thermal performance, with some specifying less than 10%.
Stencil Aperture Patterns
IPC-7093 recommends segmented stencil aperture patterns for thermal pads rather than single solid apertures. Common patterns include:
Pattern Type
Description
Void Reduction Mechanism
Window Pane
Grid of rectangular apertures
Creates channels for volatile escape
Cross-Hatch
Diagonal grid pattern
Multiple escape paths
Dot Array
Matrix of circular apertures
Distributed paste deposits
Segmented Bars
Parallel rectangular strips
Directional escape channels
The principle behind all segmented patterns is creating pathways for flux volatiles to escape during reflow. IPC-7093 recommends paste coverage of 50-80% of the thermal pad area, reduced from what a solid aperture would provide.
Via-in-Pad Considerations
Many designs place thermal vias directly in the thermal pad to improve heat transfer to inner layers or the opposite board surface. IPC-7093 addresses the challenges this creates:
Filled and capped vias are preferred to prevent solder wicking into the via barrel during reflow. If open vias must be used, via diameter should be small enough (typically ≤0.3mm) to prevent excessive solder loss. Via placement should consider interaction with stencil aperture patterns—vias in paste channels can create additional voiding. Some designs intentionally use via-in-pad to allow volatile escape, but this requires careful balancing.
Paste Volume Ratio
A critical cause of QFN floating is excessive solder paste on the thermal pad relative to perimeter pads. During reflow, the larger paste volume on the thermal pad becomes molten first, creating buoyancy that lifts perimeter terminals away from their pads.
IPC-7093 addresses this by recommending careful balancing of paste volumes. The thermal pad aperture reduction (to 50-80% coverage) partially addresses this, but designers must verify that total paste volume ratios won’t cause floating. Some assemblers further reduce thermal pad paste volume or use a stepped stencil with reduced thickness over the thermal pad area.
Assembly Process Guidelines
IPC-7093 provides process guidance beyond design, recognizing that successful BTC assembly requires proper execution throughout the assembly flow.
Solder Paste Requirements
The standard recommends solder paste thickness of 100-125 microns (4-5 mils) for perimeter pads to achieve adequate standoff height after reflow. Target standoff is approximately 50-75 microns (2-3 mils). Insufficient paste results in low standoff that can trap flux residues; excessive paste increases voiding and floating risk.
For thermal pads, IPC-7093 acknowledges that paste formulation significantly affects voiding. Flux chemistry, volatile content, and rheology all influence void formation. The standard recommends qualifying paste performance with specific component and board combinations rather than relying solely on paste specifications.
Reflow Profile Considerations
IPC-7093 notes that reflow profile optimization can reduce voiding, though results vary by paste formulation. Key considerations include adequate soak time for volatile evolution before reaching liquidus, controlled time above liquidus to allow void coalescence and escape, and peak temperature sufficient for good wetting without excessive thermal stress.
The standard acknowledges that mixed assemblies containing BTCs alongside other components may have conflicting profile requirements, requiring careful optimization.
Standoff Height
Proper standoff height is critical for BTC reliability. IPC-7093 specifies target standoff of approximately 50 microns (2 mils) for perimeter terminals. Standoff below this level can trap flux residues, creating reliability risks. Standoff significantly above this level may indicate insufficient solder volume or wetting issues.
Inspection Requirements for BTCs
The inability to visually inspect BTC solder joints is a fundamental challenge that IPC-7093 addresses directly.
X-Ray Inspection
X-ray inspection is essential for BTC quality verification. IPC-7093 provides guidance on using X-ray to evaluate joint quality, detect voiding in thermal pads, identify bridging between terminals, and assess solder coverage on perimeter pads.
The standard notes that 2D X-ray has limitations—features within the package (die, wire bonds, lead frame) can shadow solder joints, making interpretation difficult. 3D X-ray (computed tomography) provides better visualization by isolating the solder joint plane from overlying structures.
Void Measurement
For thermal pad voiding, IPC-7093 references methodologies for void percentage calculation. The standard notes that via-in-pad designs complicate void measurement since vias appear similar to voids in 2D X-ray images. Proper measurement requires either via location compensation or 3D imaging that can distinguish vias from true voids.
Visual Inspection Limitations
IPC-7093 acknowledges that visual inspection per IPC-A-610 has limited applicability to BTCs. Side solder fillets may or may not form depending on terminal construction—some suppliers provide wettable flanks while others do not. The standard references IPC-A-610 and J-STD-001 for acceptance criteria while noting their limitations for BTCs.
Rework Challenges and Guidelines
BTC rework presents unique challenges that IPC-7093 addresses:
Removal Difficulties
The low profile and lack of accessible leads make BTC removal difficult. Hot air rework requires specialized nozzles matched to package size. The large thermal pad acts as a heat sink, requiring significant energy input. Risk of PCB pad damage is higher than with leaded components.
Replacement Challenges
Site preparation after removal must ensure flat, clean pad surfaces. Solder paste application to individual sites requires precision dispensing or mini-stencils. Proper paste volume is critical—too much causes the same voiding issues as initial assembly. Local reflow must achieve proper wetting without damaging adjacent components.
IPC-7093 notes that rework capability is a key factor in supplier and process qualification for high-reliability applications.
IPC-7093 Compared to Related Standards
Understanding how IPC-7093 fits within the IPC standards ecosystem helps you apply the right document for specific needs.
IPC-7093 explicitly references these standards and provides BTC-specific interpretation and supplemental guidance where generic standards fall short.
Who Needs IPC-7093?
PCB Designers
Designers creating layouts with QFN, DFN, or LGA components need IPC-7093 for land pattern guidance, thermal pad design, and via-in-pad recommendations. The standard helps prevent design decisions that create downstream assembly problems.
Process Engineers
SMT process engineers use IPC-7093 for stencil design, reflow profile optimization, and troubleshooting assembly defects. The standard’s practical guidance on voiding reduction and floating prevention directly addresses common production issues.
Quality Engineers
Quality personnel reference IPC-7093 for inspection requirements, void acceptance guidelines, and understanding what constitutes acceptable BTC solder joints when visual inspection is limited.
Reliability Engineers
Engineers evaluating BTC reliability use IPC-7093 to understand how design and process choices affect long-term performance. The standard addresses reliability concerns unique to leadless packages.
How to Access IPC-7093
Purchase Options
Source
Format
Price (Non-Member)
IPC Official Store (shop.ipc.org)
PDF (DRM protected)
$183-215
ANSI Webstore
PDF
$190
Accuris/Techstreet
PDF
$185-200
GlobalSpec
Reference access
Varies
Version Information
IPC-7093A (October 2020) is the current revision, significantly updating the original 2011 release with expanded coverage of inspection, updated design guidance, and improved process recommendations based on industry experience.
Frequently Asked Questions About IPC-7093
What void percentage is acceptable for QFN thermal pads?
IPC-7093 does not specify a universal void acceptance criterion for thermal pads—this differs from BGA specifications in IPC-A-610. The standard references that thermal performance degrades as voiding increases, but acceptable levels depend on application requirements. Current industry work by IPC task groups suggests voiding under 50% maintains acceptable thermal performance for most applications, with many high-reliability applications requiring under 25%. Automotive applications often specify under 10%. Your acceptance criteria should be based on thermal simulation and reliability requirements for your specific application.
How does IPC-7093 differ from IPC-7351 for land patterns?
IPC-7351 provides generic land pattern calculation methods applicable to all surface mount components, while IPC-7093 provides BTC-specific guidance. The key differences are in protrusion values (IPC-7093 specifies minimal protrusions appropriate for terminals embedded in mold compound), thermal pad design (IPC-7351 doesn’t address segmented stencil patterns or void mitigation), and tolerance handling (IPC-7093 provides BTC-specific guidance on MMC/LMC conversions). Use IPC-7351 for general land pattern methodology and IPC-7093 for BTC-specific refinements.
Does IPC-7093 cover LGA packages without thermal pads?
Yes, IPC-7093 covers all bottom termination packages including LGAs that have array pad patterns without central thermal pads. The design and inspection guidance for perimeter/array pads applies regardless of whether a thermal pad is present. LGA-specific considerations include array pitch requirements, paste volume per pad, and the even greater inspection challenges posed by pads fully hidden under the package body.
How do I reduce voiding under QFN thermal pads?
IPC-7093 recommends several approaches: use segmented stencil apertures (window pane, cross-hatch) to create volatile escape channels; target 50-80% paste coverage rather than 100%; consider via-in-pad for volatile escape (with appropriate via design); optimize reflow profile for adequate soak time; and qualify low-voiding solder paste formulations. Often, multiple approaches must be combined. The standard emphasizes that voiding behavior varies significantly between component designs, so qualification testing with your specific components is essential.
Is IPC-7093 applicable for lead-free assembly?
Absolutely. IPC-7093 addresses both tin-lead and lead-free assembly processes. The standard notes that lead-free assembly typically shows higher voiding than tin-lead due to higher reflow temperatures (more volatile evolution) and higher surface tension of SAC alloys (making void escape more difficult). The design and process recommendations in IPC-7093 are even more critical for lead-free assembly where these challenges are exacerbated.
Conclusion: Implementing IPC-7093 in Your Operations
Bottom termination components aren’t going away—their benefits in size, thermal performance, and electrical characteristics make them essential for modern electronics. But successful implementation requires understanding and addressing their unique challenges.
IPC-7093 provides the comprehensive guidance needed to design for manufacturability and achieve consistent, high-quality assembly results. My recommendations for implementation:
Start with design—proper land patterns and thermal pad design prevent assembly problems before they occur
Qualify your stencil designs—test segmented aperture patterns with your specific components and paste
Invest in X-ray capability—you cannot reliably inspect BTCs without it
Establish void acceptance criteria—define requirements based on your application’s thermal and reliability needs
Train your team—ensure designers, process engineers, and quality personnel understand BTC-specific requirements
The QFN and related packages will continue growing in adoption as electronics demand smaller, higher-performance solutions. Engineers who master BTC design and assembly—guided by IPC-7093—will be well-positioned to deliver reliable products in this demanding environment.
Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.
Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.
Notes: For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.
