Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.
Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.
Notes: For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.
IPC-7091: Complete Guide to 3D Component Design & Assembly Standard
If you’ve been tasked with implementing 3D packaging in your next product design, you’ve probably realized that the learning curve is steep. Stacked die, Package-on-Package, through-silicon vias, interposers—the terminology alone can be overwhelming. That’s exactly why IPC-7091 exists, and why every engineer working with advanced packaging needs to understand it.
In this guide, I’ll walk you through everything IPC-7091 covers, from its scope and key topics to practical applications. Having worked through numerous 3D packaging projects, I can tell you this standard is the most comprehensive industry resource for navigating the complexities of 3D component technology.
What Is IPC-7091?
IPC-7091, officially titled “Design and Assembly Process Implementation of 3D Components,” is a 96-page industry standard developed by IPC’s 3D Electronic Packages Guideline Task Group (B-11a). First published in June 2017 with Revision A released in January 2023, IPC-7091 provides practical guidance for designing, developing, and assembling 3D-packaged semiconductor components.
Unlike narrow standards that focus on a single aspect of packaging, IPC-7091 takes a holistic approach. It addresses the entire ecosystem of 3D packaging—from interposer design and substrate considerations to board-level assembly, inspection, and repair. The standard recognizes that 3D packaging isn’t just about stacking chips; it’s about managing complex interactions between die elements, thermal paths, assembly processes, and reliability requirements.
The 3D semiconductor packages covered by IPC-7091 may include multiple die elements (both homogeneous and heterogeneous), discrete passive SMT devices that are either surface mounted or embedded within the substrate structure, and various interconnect technologies from wire bonding to through-silicon vias.
Why IPC-7091 Matters in Today’s Market
The 3D IC and 2.5D IC packaging market has experienced explosive growth, valued at approximately $60 billion in 2024 with projections reaching $120-170 billion by 2032-2034. This represents a compound annual growth rate exceeding 10%, driven by applications that demand performance levels impossible to achieve with traditional 2D packaging.
Several market forces make IPC-7091 increasingly relevant for design and manufacturing teams.
The AI and HPC Revolution
High-performance computing and AI applications captured 38% of the 3D IC packaging market revenue in 2024. These applications require the bandwidth and density that only 3D packaging can deliver. TSMC is scaling its CoWoS (Chip on Wafer on Substrate) capacity to 88,000 wafers per month by 2026 to keep pace with demand from AI accelerator manufacturers.
Memory Integration Requirements
Memory applications, dominated by High Bandwidth Memory (HBM) stacks, accounted for 41% of the 3D IC packaging market in 2024. HBM technology, which stacks multiple DRAM die using through-silicon vias, delivers bandwidth exceeding 1 TB/s—essential for feeding data-hungry AI processors. The upcoming HBM4+ generation is driving a projected 24.91% CAGR for memory-centric packages through 2030.
Miniaturization Demands
Consumer electronics, automotive ADAS, and IoT applications continue pushing for smaller form factors with greater functionality. 3D packaging enables designers to integrate more capability in less space, extending product possibilities in wearables, mobile devices, and autonomous systems.
IPC-7091 provides the standardized framework for engineers navigating these demanding applications.
Key Topics Covered in IPC-7091
IPC-7091 is organized to address the complete lifecycle of 3D component implementation. Here’s what the standard covers:
One of IPC-7091’s most valuable contributions is establishing clear definitions for 3D packaging terminology. The standard defines the dimensional hierarchy that often confuses engineers new to advanced packaging:
Package Type
Definition
Key Characteristics
2D Package
Single die on substrate
Traditional flip chip or wire bond
2.5D Package
Multiple die side-by-side on interposer
Dies connected through silicon/glass/organic interposer with TSV
3D Package
Vertically stacked die
Die-on-die stacking with direct interconnection
PoP
Stacked packages
Complete packages stacked and interconnected
SiP
System in Package
Multiple die/components in single package forming complete system
3D Packaging Technologies Explained
IPC-7091 addresses the full spectrum of 3D integration approaches. Understanding these technologies helps you select the right approach for your application.
Package-on-Package (PoP)
PoP stacks complete, tested packages rather than bare die. The bottom package typically contains a logic device (processor, SoC), while the top package contains memory. This approach offers significant advantages including the ability to separately test logic and memory before stacking (improving overall yield), supply chain flexibility allowing different memory suppliers, and simplified logistics since packages can be sourced and qualified independently.
PoP has been widely deployed since Sony’s PlayStation Portable in 2004 and remains popular in mobile devices. IPC-7091 covers PoP fluxing processes, die gap specifications, and z-height control—critical parameters for successful PoP assembly.
Stacked Die Packaging
Stacked die technology places multiple bare die within a single package, connected by wire bonds or through-silicon vias. Amkor and other OSAT providers have demonstrated up to 24 die stacks, though most production implementations use 2-9 die. IPC-7091 addresses the unique challenges of stacked die including die thinning requirements, adhesive selection, wire bond loop height control, and thermal management in dense stacks.
2.5D Interposer Integration
2.5D technology places multiple die side-by-side on a silicon, glass, or organic interposer. The interposer provides ultra-fine-pitch routing between die—far finer than possible on organic substrates. Through-silicon vias (TSVs) connect the top surface to BGA connections on the bottom.
This approach is dominant in high-performance applications. TSMC’s CoWoS platform, used by NVIDIA and AMD for AI accelerators, is a prime example. IPC-7091 covers interposer design considerations, TSV formation processes, and the integration challenges unique to 2.5D configurations.
True 3D IC Integration
True 3D ICs stack die vertically with direct die-to-die connections, often using hybrid bonding (copper-to-copper direct bonding) rather than solder bumps. This approach delivers the shortest interconnect paths and highest integration density but presents significant thermal and manufacturing challenges.
IPC-7091 addresses 3D IC considerations including fusion bonding processes, intermetallic bond formation, and the reliability implications of highly integrated stacks.
Through-Silicon Via (TSV) Technology
TSVs are fundamental to advanced 3D packaging, and IPC-7091 dedicates significant attention to this technology. TSVs are vertical electrical connections that pass completely through a silicon die or interposer, enabling connections between stacked layers or between the top and bottom surfaces of an interposer.
The standard covers critical TSV parameters including aspect ratio (depth-to-diameter ratio), which affects fill quality and electrical performance; TSV pitch and density, determining achievable interconnect density; liner and barrier materials preventing copper diffusion into silicon; and fill materials, typically copper, tungsten, or polysilicon.
Thermal Management in 3D Packages
Thermal management is perhaps the greatest challenge in 3D packaging, and IPC-7091 provides extensive guidance. When you stack multiple active die, heat generated in upper die must pass through lower die to reach the heat sink. This creates thermal gradients that impact reliability and performance.
Heat Transfer Paths
IPC-7091 addresses multiple thermal management approaches including conductive cooling through die stack and substrate, thermal interface materials between die and heat spreaders, liquid cooling systems for high-power applications, and thermal vias in substrates and interposers.
The standard provides guidance on thermal simulation and the selection of appropriate cooling technologies based on power density requirements.
IPC-7091 Compared to Related Standards
Understanding how IPC-7091 fits within the broader standards ecosystem helps you reference the right documents for specific needs.
Standard
Focus
Relationship to IPC-7091
IPC-7094
Design and Assembly for Flip Chip and Die-Size Components
Covers flip chip specifically; IPC-7091 extends to 3D stacking
J-STD-012
Implementation of Flip Chip and Chip Scale Technology
Use IPC-7091 when you’re implementing any form of 3D packaging—PoP, stacked die, interposer-based, or embedded die technologies. The standard is your primary reference for design rules, assembly processes, and reliability considerations specific to 3D.
Use IPC-7094 when your focus is specifically on flip chip die attachment without 3D stacking. IPC-7094 provides deeper coverage of flip chip bump technology and assembly.
Use J-STD-012 for a broader technology overview of flip chip and CSP. It’s more educational in nature, while IPC-7091 is more prescriptive for 3D implementation.
Who Needs IPC-7091?
IPC-7091 explicitly identifies its target audience as managers, design/process engineers, and operators dealing with 3D semiconductor packaging implementation, interposer/substrate/PWB design, and board-level assembly/inspection/repair processes.
Specific Roles That Benefit
Package Design Engineers use IPC-7091 for design rules, stack-up considerations, and thermal management guidelines when creating 3D package designs.
PCB Design Engineers reference the standard for understanding how 3D components interface with their boards, including land pattern requirements and routing considerations.
Assembly Process Engineers find guidance on PoP assembly, reflow profiles, underfill dispensing, and process control for 3D components.
Quality Engineers use IPC-7091 for inspection criteria, acceptance standards, and reliability test requirements specific to 3D packages.
Reliability Engineers reference the standard for understanding failure modes, qualification test requirements, and design-for-reliability considerations in 3D packaging.
Practical Applications of IPC-7091
Design Phase Implementation
During the design phase, IPC-7091 provides guidance on interposer material selection (silicon, glass, organic) based on application requirements. The standard helps engineers determine appropriate TSV dimensions and density for required electrical performance, establish thermal management strategies early in the design cycle, and select appropriate package outline standards for compatibility.
Manufacturing Process Development
For manufacturing, IPC-7091 addresses PoP fluxing process control and statistical monitoring, die attach procedures for stacked configurations, reflow profile development for complex 3D assemblies, and underfill material selection and dispensing methods.
Inspection and Quality Control
The standard provides criteria for visual inspection of 3D assemblies, guidance on X-ray inspection for hidden interconnects, acceptance criteria for solder joint quality in PoP and stacked die, and rework procedures using convection and laser soldering.
How to Access IPC-7091
Purchase Options
Source
Format
Price (Non-Member)
IPC Official Store (shop.ipc.org)
PDF (DRM protected)
$215
ANSI Webstore
PDF
$200-215
Techstreet/Accuris
PDF
$200-215
Version Information
The current revision is IPC-7091A, published January 2023, which expanded the original 108-page 2017 release to 96 pages (reorganized). The revision updated content for current technologies including HBM, EMIB (Embedded Multi-Die Interconnect Bridge), and advanced interposer approaches.
Frequently Asked Questions About IPC-7091
What is the difference between IPC-7091 and IPC-7094?
IPC-7094 focuses specifically on flip chip and die-size component design and assembly—essentially 2D flip chip technology. IPC-7091 extends beyond flip chip to cover the full spectrum of 3D packaging including Package-on-Package (PoP), stacked die, interposer-based integration, and embedded die technologies. If your design involves any form of vertical integration or 3D stacking, IPC-7091 is the appropriate reference. If you’re implementing traditional flip chip without stacking, IPC-7094 may be sufficient.
Does IPC-7091 cover through-silicon via (TSV) specifications?
Yes, IPC-7091 provides extensive coverage of TSV technology. The standard addresses TSV formation processes (via-first, via-middle, via-last), via filling methods, and the use of TSVs in both silicon interposers and stacked die configurations. It also covers through-glass vias (TGV) for glass interposer applications. However, for detailed TSV process specifications, you may also need to reference foundry-specific design rules from companies like TSMC, Samsung, or Intel.
Is IPC-7091 applicable to High Bandwidth Memory (HBM)?
Absolutely. HBM is a prime example of 3D IC technology using TSV-based die stacking. IPC-7091’s coverage of stacked die packaging, TSV interconnects, and 2.5D interposer integration directly applies to HBM implementation. The standard helps engineers understand how HBM stacks integrate with logic die on silicon interposers—the configuration used in virtually all AI accelerators and high-performance GPUs.
What assembly processes does IPC-7091 address?
IPC-7091 provides comprehensive assembly guidance covering Package-on-Package (PoP) fluxing processes and flux height control, die attach procedures for stacked configurations, reflow soldering profiles for 3D assemblies, underfill material selection and application methods, and rework procedures using both convection and laser soldering. The standard addresses both the unique challenges of 3D assembly (such as managing multiple reflow cycles) and conventional SMT considerations.
How does IPC-7091 address thermal management?
Thermal management receives significant attention in IPC-7091, recognizing it as the primary challenge in 3D packaging. The standard covers heat transfer path analysis for stacked configurations, thermal interface material selection, active cooling technologies including liquid cooling, thermal via implementation in substrates and interposers, and guidance on thermal simulation approaches. The standard helps engineers understand how heat flows through 3D stacks and design appropriate thermal solutions.
Conclusion: Implementing IPC-7091 in Your Organization
The 3D packaging market is growing at over 10% annually, driven by AI, HPC, 5G, and automotive applications that demand performance levels impossible with traditional packaging. For organizations implementing these technologies, IPC-7091 provides the standardized framework for success.
My recommendations for getting started with IPC-7091:
Assess your 3D packaging needs to determine which sections of IPC-7091 are most relevant—PoP assembly, interposer design, or full 3D IC integration.
Train your team on IPC-7091 requirements, particularly design engineers, process engineers, and quality personnel who will work with 3D components.
Integrate IPC-7091 into your design reviews to ensure 3D packaging considerations are addressed early in the development cycle.
Reference IPC-7091 in supplier specifications when sourcing 3D components or outsourcing assembly to ensure consistent expectations.
Stay current with revisions—the 2023 update to IPC-7091A reflects significant technology evolution, and future revisions will address emerging technologies like hybrid bonding and advanced chiplet integration.
As Moore’s Law scaling becomes increasingly difficult and expensive, advanced packaging—and 3D integration specifically—offers a path to continued performance improvement. IPC-7091 is your guide to navigating this complex but rewarding technology landscape.
Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.
Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.
Notes: For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.
