The XC2C128-7CP132C is a high-performance Complex Programmable Logic Device (CPLD) from the Xilinx CoolRunner-II family. This ultra-low power CPLD delivers exceptional performance with 128 macrocells, 7ns pin-to-pin propagation delay, and operates at 152MHz frequency. Designed for commercial-grade applications, this device is ideal for portable electronics, communication equipment, and industrial control systems requiring reliable programmable logic solutions.
XC2C128-7CP132C Key Features and Benefits
The CoolRunner-II architecture combines high-speed performance with industry-leading power efficiency. Engineers choose this device for applications where both speed and power consumption are critical design factors.
Ultra-Low Power Consumption
The XC2C128-7CP132C features Xilinx’s proprietary zero-power technology, drawing as low as 13µA quiescent current. This makes it perfect for battery-powered devices and energy-conscious designs where standby power must be minimized.
High-Speed Performance
With pin-to-pin delays of just 7ns and a maximum operating frequency of 152MHz, the XC2C128-7CP132C delivers the speed required for demanding digital logic applications without compromising power efficiency.
Flexible I/O Voltage Support
The device supports multi-voltage I/O operation from 1.5V to 3.3V, enabling seamless interfacing with various logic families and voltage domains within the same system.
XC2C128-7CP132C Technical Specifications
| Parameter |
Specification |
| Manufacturer |
Xilinx (AMD) |
| Product Family |
CoolRunner-II CPLD |
| Part Number |
XC2C128-7CP132C |
| Number of Macrocells |
128 |
| Equivalent Gate Count |
3,000 Gates |
| Maximum User I/O Pins |
100 |
| Operating Frequency |
152 MHz |
| Pin-to-Pin Delay (tPD) |
7 ns |
| Core Voltage (VCC) |
1.8V |
| I/O Voltage Range |
1.5V to 3.3V |
| Process Technology |
0.18µm CMOS |
| Package Type |
132-Ball CSBGA (Chip Scale BGA) |
| Package Dimensions |
8mm x 8mm |
| Ball Pitch |
0.5mm |
| Temperature Range |
Commercial (0°C to +70°C) |
| Quiescent Current |
13µA (Typical) |
XC2C128-7CP132C Package Information
| Attribute |
Value |
| Package Style |
Chip Scale Ball Grid Array (CSBGA) |
| Total Pin Count |
132 Balls |
| User I/O Count |
100 |
| Package Body Size |
8mm x 8mm |
| Ball Pitch |
0.5mm |
| Mounting Type |
Surface Mount (SMD) |
| Lead-Free Options |
Available (RoHS Compliant versions) |
XC2C128-7CP132C Supported I/O Standards
The CoolRunner-II 128-macrocell CPLD supports multiple JEDEC I/O standards for maximum design flexibility:
| I/O Standard |
Output VCCIO |
Input VCCIO |
Description |
| LVTTL |
3.3V |
3.3V |
Low Voltage TTL |
| LVCMOS33 |
3.3V |
3.3V |
Low Voltage CMOS 3.3V |
| LVCMOS25 |
2.5V |
2.5V |
Low Voltage CMOS 2.5V |
| LVCMOS18 |
1.8V |
1.8V |
Low Voltage CMOS 1.8V |
| LVCMOS15 |
1.5V |
1.5V |
Low Voltage CMOS 1.5V |
| HSTL_I |
1.5V |
1.5V |
High-Speed Transceiver Logic |
| SSTL2_I |
2.5V |
2.5V |
Stub Series Terminated Logic II |
| SSTL3_I |
3.3V |
3.3V |
Stub Series Terminated Logic III |
CoolRunner-II CPLD Architecture Overview
Advanced Interconnect Matrix (AIM)
The XC2C128-7CP132C features eight Function Blocks interconnected by the low-power Advanced Interconnect Matrix. The AIM provides 40 true and complement inputs to each Function Block, enabling efficient signal routing with minimal power consumption.
Function Block Structure
Each Function Block contains a 40 by 56 product-term PLA (Programmable Logic Array) and 16 macrocells. The macrocells feature numerous configuration bits supporting both combinational and registered modes of operation.
Power Management Features
- DataGATE Technology: Reduces dynamic power by blocking signal transitions to inactive portions of the CPLD
- CoolCLOCK Technology: Combines clock gating with clock division for additional power savings
- Zero Power Mode: Ultra-low standby current for battery-powered applications
XC2C128-7CP132C Programming and Development
In-System Programming (ISP)
The device supports fastest in-system programming using the IEEE 1532 (JTAG) standard. This enables convenient field updates and rapid prototyping without removing the device from the circuit board.
JTAG Boundary Scan
Full IEEE 1149.1 boundary scan compliance provides comprehensive testing and debugging capabilities during development and production.
Development Tools
- Xilinx ISE Design Suite: Complete development environment for synthesis, implementation, and programming
- Xilinx Vivado Design Suite: Modern design tool with enhanced synthesis capabilities
- Third-Party Synthesis Tools: Compatible with industry-standard HDL compilers
XC2C128-7CP132C Applications
The XC2C128-7CP132C CPLD is ideal for a wide range of applications:
Consumer Electronics
- Portable devices requiring instant-on capability
- Battery-powered equipment with strict power budgets
- Mobile phone accessories and peripherals
Communications Equipment
- Interface bridging and protocol conversion
- Clock management and distribution
- Glue logic for high-speed data paths
Industrial Control Systems
- Real-time control logic implementation
- Sensor interface and signal conditioning
- Motor control and automation systems
Embedded Systems
- Microcontroller peripheral expansion
- Address decoding and memory interfacing
- Boot sequencing and power management logic
Why Choose XC2C128-7CP132C for Your Design?
Instant-On Operation
Unlike FPGAs that require external configuration memory, the CoolRunner-II CPLD stores configuration in internal flash memory, enabling immediate operation upon power-up.
Pin Compatibility
The XC2C128 maintains pin compatibility with other densities in the CoolRunner-II family, simplifying design migration and allowing easy capacity scaling.
Reliable Performance
The 0.18µm CMOS technology ensures consistent performance across the commercial temperature range with excellent noise immunity and signal integrity.
Related Xilinx Programmable Logic Devices
Looking for alternative CPLD and FPGA solutions? Explore our complete selection of Xilinx FPGA devices including Spartan, Artix, Kintex, and Virtex families for higher-density programmable logic requirements.
XC2C128-7CP132C Ordering Information
| Part Number |
Speed Grade |
Package |
Temperature |
Status |
| XC2C128-7CP132C |
-7 (7ns) |
132-CSBGA |
Commercial (0°C to +70°C) |
Active |
| XC2C128-7CP132I |
-7 (7ns) |
132-CSBGA |
Industrial (-40°C to +85°C) |
Active |
| XC2C128-6CP132C |
-6 (5.7ns) |
132-CSBGA |
Commercial (0°C to +70°C) |
Active |
| XC2C128-7CPG132C |
-7 (7ns) |
132-CSBGA (Pb-Free) |
Commercial (0°C to +70°C) |
Active |
Frequently Asked Questions About XC2C128-7CP132C
What is the difference between XC2C128-7CP132C and XC2C128-6CP132C?
The primary difference is the speed grade. The -7 variant offers 7ns pin-to-pin delay at 152MHz, while the -6 variant provides faster 5.7ns timing at 263MHz but with higher power consumption.
Is the XC2C128-7CP132C RoHS compliant?
The standard XC2C128-7CP132C uses leaded solder balls. For RoHS-compliant applications, order the XC2C128-7CPG132C variant with lead-free packaging.
What programming cable is required for the XC2C128-7CP132C?
The device can be programmed using Xilinx Platform Cable USB or compatible JTAG programmers supporting IEEE 1149.1/1532 standards.
Can the XC2C128-7CP132C operate at 3.3V I/O while the core runs at 1.8V?
Yes, the CoolRunner-II architecture supports independent I/O voltage banks, allowing 3.3V I/O interfacing with the 1.8V core voltage for maximum design flexibility.
