The XCZU28DR-1FFVG1517I is a high-performance RF System-on-Chip (RFSoC) from Xilinx’s Zynq UltraScale+ family. This advanced device integrates RF data converters, programmable logic, and a powerful processing system into a single chip. Engineers designing software-defined radios, 5G wireless infrastructure, and radar systems rely on this component for exceptional signal processing performance.
Key Features of the XCZU28DR-1FFVG1517I RFSoC
The XCZU28DR-1FFVG1517I combines multiple high-speed RF-ADCs and RF-DACs with a quad-core Arm Cortex-A53 processor. This integration eliminates the need for external data converter chips. As a result, designers can reduce board space, lower power consumption, and simplify system architecture.
This Xilinx FPGA device belongs to the Gen 1 RFSoC family. It supports direct RF sampling up to 4 GHz input frequency. The industrial temperature grade (-40°C to +100°C) makes it suitable for demanding environments.
XCZU28DR-1FFVG1517I Technical Specifications
RF Data Converter Specifications
| Parameter |
Specification |
| RF-ADC Channels |
8 channels |
| RF-ADC Resolution |
12-bit |
| RF-ADC Sample Rate |
Up to 4.096 GSPS |
| RF-DAC Channels |
8 channels |
| RF-DAC Resolution |
14-bit |
| RF-DAC Sample Rate |
Up to 6.554 GSPS |
| Maximum RF Input Frequency |
4 GHz |
| DDC per RF-ADC |
1 |
| Decimation/Interpolation |
1x, 2x, 4x, 8x |
Processing System Specifications
| Component |
Details |
| Application Processing Unit (APU) |
Quad-core Arm Cortex-A53 @ 1.3 GHz |
| Real-Time Processing Unit (RPU) |
Dual-core Arm Cortex-R5F @ 600 MHz |
| L1 Cache (APU) |
32KB instruction + 32KB data per core |
| L2 Cache (APU) |
1 MB shared with ECC |
| On-Chip Memory |
256 KB with ECC |
| Floating Point Support |
Single and double precision |
Programmable Logic Resources
| Resource |
Quantity |
| System Logic Cells |
930,300 |
| CLB Flip-Flops |
850,560 |
| CLB LUTs |
425,280 |
| Block RAM |
38.0 Mb (1,080 blocks) |
| UltraRAM |
22.5 Mb (80 blocks) |
| DSP Slices |
4,272 |
| Distributed RAM |
13.0 Mb |
High-Speed Connectivity
| Interface |
Specification |
| GTY Transceivers |
16 channels |
| GTY Data Rate |
Up to 28.21 Gb/s |
| PS-GTR Transceivers |
4 channels |
| PCIe Support |
Gen3 x16 (2 blocks) |
| 100G Ethernet |
2 blocks with RS-FEC |
| 150G Interlaken |
1 block |
Package and Environmental Specifications
| Parameter |
Value |
| Package Type |
FFVG1517 (Flip-chip BGA) |
| Package Dimensions |
40 mm × 40 mm |
| Ball Pitch |
1.0 mm |
| Total Pins |
1517 |
| High-Performance I/O (HP) |
299 |
| High-Density I/O (HD) |
48 |
| Speed Grade |
-1 (Standard) |
| Temperature Grade |
Industrial (-40°C to +100°C) |
| VCCINT Operating Voltage |
0.85V |
Soft Decision Forward Error Correction (SD-FEC)
The XCZU28DR-1FFVG1517I includes 8 SD-FEC blocks for advanced error correction. These blocks support both LDPC and Turbo decoding modes.
SD-FEC Capabilities
| Feature |
Specification |
| SD-FEC Blocks |
8 |
| LDPC Decode/Encode |
Yes |
| Turbo Decode |
Yes |
| Supported Standards |
5G NR, LTE, DOCSIS 3.1 |
| Maximum Iterations |
1-63 (configurable per codeword) |
| Code Configuration |
Up to 128 codes |
The LDPC encoder and decoder enable high-throughput error correction for 5G wireless and backhaul applications. Meanwhile, Turbo decoding supports legacy LTE systems. This flexibility allows a single platform to address multiple wireless standards.
Applications for XCZU28DR-1FFVG1517I
The XCZU28DR-1FFVG1517I excels in applications requiring direct RF sampling and high-performance signal processing.
Primary Applications
- 5G Wireless Infrastructure: Massive MIMO base stations and small cells
- Software-Defined Radio (SDR): Multi-band, multi-mode radio platforms
- Radar and Electronic Warfare: Phased array systems and signal intelligence
- Test and Measurement: High-speed data acquisition systems
- Cable Infrastructure: DOCSIS 3.1 remote PHY devices
- Satellite Communications: Ground station equipment
Why Choose This RFSoC?
The integration of RF converters with programmable logic reduces the component count significantly. Traditional designs require separate ADC chips, DAC chips, and FPGA devices. This RFSoC combines all these functions on a single die. Therefore, engineers achieve lower latency, reduced power consumption, and smaller form factors.
Memory Interface Support
The XCZU28DR-1FFVG1517I provides comprehensive memory interface options for demanding applications.
Supported Memory Standards
| Memory Type |
Maximum Data Rate |
| DDR4 |
2400 Mb/s |
| DDR3/DDR3L |
Supported |
| LPDDR4 |
32-bit bus width |
| LPDDR3 |
Supported |
| Maximum DRAM Capacity |
32 GB |
The dynamic memory controller supports 64-bit bus width with optional ECC protection. This ensures data integrity in mission-critical applications.
I/O Peripheral Integration
The processing system includes extensive peripheral connectivity options.
Available Peripherals
| Peripheral |
Quantity/Details |
| Gigabit Ethernet MAC |
4 (Triple-speed 10/100/1000 Mb/s) |
| USB 3.0 Controllers |
2 |
| USB 2.0 Controllers |
2 |
| SD/SDIO 3.0 Controllers |
2 |
| UART |
2 |
| SPI |
2 |
| I2C |
2 |
| CAN 2.0B |
2 |
| GPIO |
Up to 174 bits (78 MIO + 96 EMIO) |
These peripherals enable system integration without additional interface chips. The MIO (Multiplexed I/O) pins provide flexible pin assignment for optimal board layout.
Security Features
The XCZU28DR-1FFVG1517I includes robust security capabilities for protecting intellectual property and ensuring secure boot.
Security Capabilities
| Feature |
Description |
| AES-GCM Encryption |
256-bit hardware accelerator |
| SHA-3/384 |
Secure hash algorithm support |
| RSA Authentication |
4096-bit for secure boot |
| Secure Boot |
Hardware-enforced boot chain |
| eFUSE |
One-time programmable memory |
The Configuration Security Unit (CSU) manages all cryptographic operations. It supports both secure and non-secure boot modes depending on system requirements.
Part Number Breakdown: XCZU28DR-1FFVG1517I
Understanding the part number helps specify the correct device for your application.
| Code |
Meaning |
| XC |
Xilinx Commercial |
| ZU |
Zynq UltraScale+ |
| 28 |
Device density index |
| D |
Quad APU + Dual RPU |
| R |
RF Signal Engine |
| -1 |
Speed grade (standard) |
| FF |
Flip-chip package |
| V |
RoHS 6/6 compliant |
| G |
Package designator |
| 1517 |
Pin count |
| I |
Industrial temperature grade |
Development Tools and Support
Xilinx provides comprehensive development tools for the XCZU28DR-1FFVG1517I.
Available Tools
- Vivado Design Suite: Hardware design and implementation
- Vitis Software Platform: Embedded software development
- PetaLinux Tools: Linux BSP generation
- RFSoC Evaluation Kits: Hardware prototyping platforms
The tools include reference designs for common applications like digital radio and MIMO systems. These accelerate development time significantly.
Ordering Information Summary
| Part Number |
Description |
| XCZU28DR-1FFVG1517I |
Industrial temp, -1 speed grade, FFVG1517 package |
| XCZU28DR-2FFVG1517I |
Industrial temp, -2 speed grade, FFVG1517 package |
| XCZU28DR-1FFVG1517E |
Extended temp, -1 speed grade, FFVG1517 package |
| XCZU28DR-2FFVG1517E |
Extended temp, -2 speed grade, FFVG1517 package |
Conclusion
The XCZU28DR-1FFVG1517I delivers exceptional performance for RF signal processing applications. Its integrated RF-ADCs, RF-DACs, and programmable logic simplify system design. The quad-core Arm processor handles complex algorithms while the FPGA fabric provides hardware acceleration. This combination makes the XCZU28DR-1FFVG1517I an ideal choice for next-generation wireless infrastructure, defense systems, and advanced instrumentation.
For more information about this and other RFSoC devices, explore our complete selection of programmable logic solutions.
