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Notes: For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.
Multi-Layer Metal Core PCB Design: Bergquist HT-09009 & CML-11006 Applications
Most engineers encountering metal core PCB for the first time associate it with a single copper layer — a simple LED pad, a power device footprint, a straightforward single-sided aluminium board. That mental model handles perhaps 80% of MCPCB volume in production. The other 20% — the motor drive that also hosts a gate drive signal chain, the automotive lighting ECU that combines LED thermal management with PWM control logic, the industrial inverter with both a power stage and a communication interface — needs a multi-layer metal core PCB design approach, and that is where the design rules, stackup choices, and dielectric grade selection get genuinely complicated.
This article focuses on two Bergquist Thermal Clad grades that are optimised specifically for multi-layer and high-voltage MCPCB applications: HT-09009 and CML-11006. Both grades appear in the Bergquist Thermal Clad Selection Guide alongside the more commonly discussed HPL, HT-04503, HT-07006, and MP grades, but receive far less coverage in standard IMS PCB literature. Understanding why these grades exist and what design problems they solve is the point of this article. For foundational background on the complete Bergquist product line and how single-layer MCPCB is specified and sourced, start with the Bergquist PCB reference page.
Before addressing the two grades directly, it is worth being precise about what forces a design engineer toward multi-layer metal core PCB construction in the first place.
A single-layer MCPCB is the most thermally efficient IMS configuration — one copper circuit layer bonded to the dielectric, bonded to the metal base, with a direct vertical heat path from component thermal pad to substrate. This simplicity is also its constraint: every circuit element must fit on one layer, only SMD components can be used without special via isolation procedures, and there is no possibility of signal routing beneath a power plane or separating high-current power traces from low-level analog or digital signals.
In practice, real power electronics designs almost always combine at least two functions: a power stage that generates heat (the MOSFET array, the LED drive current path, the output inductor return path) and a control or signal chain that generates very little heat but requires routing flexibility, EMI separation from the power stage, and often dozens of signal nets. Trying to route both on one copper layer with a single IMS dielectric produces a crowded, compromise-heavy layout that frequently fails EMI or signal integrity qualification.
Multi-layer MCPCB design solves this by combining two or more copper circuit layers — separated by thermally conductive dielectric or FR-4 prepreg — above the metal base. The power stage components sit on the top copper layer directly above the IMS dielectric and substrate, retaining the thermal management advantage. The signal and control circuitry routes on inner layers or the secondary top layer, with interconnection via plated-through-hole vias that are isolated from the metal substrate.
The Two Stackup Philosophies: True Multi-Layer IMS vs Hybrid IMS + FR-4
Before selecting a dielectric grade for multi-layer metal core PCB design, engineers need to understand that there are two fundamentally different stackup philosophies, each with different material requirements.
True Two-Layer IMS Stackup
A true two-layer IMS stackup places two copper circuit layers above a single IMS dielectric and metal base. The stackup from top to bottom reads: copper layer 1 → thin dielectric spacer → copper layer 2 → IMS thermal dielectric → metal substrate. Both circuit layers share the same IMS core. Vias connecting the two copper layers must be designed to stop before penetrating the IMS dielectric into the metal, which requires blind vias or carefully controlled drill depth. This construction retains the thermal performance of the IMS dielectric for both circuit layers and is used in designs where both layers carry power or heat-generating devices.
Hybrid IMS + FR-4 Stackup
The hybrid approach bonds a standard FR-4 two-layer or multilayer sub-assembly onto the top face of the IMS dielectric and metal base. The FR-4 portion provides unlimited routing layers and standard via processing. The IMS base provides thermal management for the power devices, which are either mounted directly on the bottom copper of the FR-4 (with thermal vias down to the IMS dielectric) or placed in cutouts that expose the IMS surface. This is the most common multi-layer metal core PCB architecture in production because it uses standard FR-4 fabrication tools for the routing layers and only applies the IMS process to the base.
Bergquist HT-09009: The High-Voltage Multi-Layer Grade
What HT-09009 Is and Why It Exists
HT-09009 is the thickest dielectric in the standard Bergquist Thermal Clad High Temperature series. The designation encodes its key attributes: HT (high temperature), 09 (9 mils nominal thickness), 006 (not present in this grade — the copper weight specification varies). From the Bergquist Thermal Clad Selection Guide, HT-09009’s properties are:
Dielectric thickness: 9 mils / 229 µm Thermal conductivity: 2.2 W/m·K Thermal resistance: 0.16 °C·in²/W (1.03 °C·cm²/W) Breakdown voltage (AC): 20.0 kV Dielectric strength: 7 V/mil Glass transition temperature (Tg): 150 °C UL RTI (electro/mechanical): 150/150 °C Peel strength: 6 lb/in (1.1 N/mm)
The defining characteristic of HT-09009 is its breakdown voltage of 20.0 kVAC — the highest in the standard Thermal Clad range. Compare this to HT-07006 at 11.0 kVAC and HT-04503 at 11.0 kVAC. HT-09009’s dielectric is 56% thicker than HT-07006 (229 µm vs 152 µm), which is what drives both the elevated breakdown voltage and the higher thermal resistance of 0.16 vs 0.11 °C·in²/W.
When HT-09009 Is the Correct Choice
HT-09009 is specified wherever the electrical isolation requirement between the copper circuit and the metal substrate exceeds what HT-07006 can reliably provide. The practical trigger points are EV traction applications at 800 VDC bus, three-phase inverter designs at 690 VAC mains, industrial motor drives operating on 480–600 VAC lines, and any design where the hipot test specification exceeds 4–5 kVAC. The 20 kVAC breakdown voltage provides substantial safety margin against sustained high-voltage stress, partial discharge events, and the transient overvoltage conditions common in inductive switching circuits.
The UL RTI of 150/150 °C for both electrical and mechanical properties is also higher than HT-04503 and HT-07006’s 140/140 °C rating, which matters for sustained high-temperature automotive and under-hood industrial applications where continuous operating temperature approaches 140–145 °C and a 10 °C margin is insufficient for a conservative design.
Table 2: HT-09009 vs HT-07006 vs HT-04503 — Side-by-Side Comparison
Property
HT-09009
HT-07006
HT-04503
Test Method
Dielectric Thickness
9 mil / 229 µm
6 mil / 152 µm
4.5 mil / 114 µm
Per product
Thermal Conductivity
2.2 W/m·K
2.2 W/m·K
2.2 W/m·K
ASTM D5470
Thermal Resistance
0.16 °C·in²/W
0.11 °C·in²/W
0.05 °C·in²/W
ASTM D5470
Breakdown Voltage (AC)
20.0 kVAC
11.0 kVAC
11.0 kVAC
ASTM D149
Tg
150 °C
>150 °C (typically)
>170 °C
ASTM E1356
UL RTI (E/M)
150/150 °C
140/140 °C
150/150 °C
UL 746B
Max Operating Temp
150 °C
140 °C
140 °C
UL 796
Peel Strength
6 lb/in (1.1 N/mm)
6 lb/in (1.1 N/mm)
6 lb/in (1.1 N/mm)
ASTM D3165
HT-09009 in Multi-Layer Design: The Thermal Tradeoff
The tradeoff when selecting HT-09009 in a multi-layer metal core PCB design is thermal resistance. At 0.16 °C·in²/W, HT-09009 is 3× the thermal resistance of HT-04503 at 0.05 °C·in²/W. For a 10 mm × 10 mm power device pad at 10 W dissipation, the dielectric thermal resistance contribution changes from 0.8 °C/W (HT-04503) to 2.5 °C/W (HT-09009) — a 17 °C junction temperature difference at 10 W. That is not negligible.
The engineering judgement call is whether the high-voltage isolation requirement forces HT-09009 despite this thermal penalty. For 800 VDC bus EV applications, there is no alternative in the standard Bergquist range — you need the breakdown headroom and you accept the thermal resistance. In those designs, engineers compensate for the higher dielectric resistance by using copper base metal instead of aluminium (385 W/m·K vs 150 W/m·K substrate spreading), thicker copper on the circuit layer (2–3 oz to improve lateral spreading before heat enters the dielectric), and lower heatsink thermal resistance to keep total system R_θ within junction temperature limits.
Bergquist CML-11006: The Cost-Optimised Multi-Layer Grade
What CML-11006 Is and Why It Exists
CML is the Bergquist Thermal Clad grade designed for multi-layer constructions where cost optimisation is the primary driver alongside adequate thermal performance. The CML designation stands for Cost-effective Multi-Layer. From the Bergquist Thermal Clad Selection Guide, CML-11006’s properties are:
Dielectric thickness: 6 mils / 152 µm Thermal conductivity: 1.1 W/m·K Thermal resistance: 0.21 °C·in²/W (1.35 °C·cm²/W) Breakdown voltage (AC): 10.0 kVAC Dielectric strength: 7 V/mil Glass transition temperature (Tg): 90 °C UL RTI (electro/mechanical): 130/130 °C Peel strength: 10 lb/in (1.8 N/mm)
Two characteristics immediately distinguish CML-11006 from the HT grades. First, its Tg of 90 °C is dramatically lower — below the Tg of standard FR-4. Second, its peel strength of 10 lb/in (1.8 N/mm) is the highest in the Bergquist range, making it the best-bonding dielectric for complex multi-layer constructions where multiple press cycles or higher lamination stresses are involved. The CML grade’s lower Tg is the cost enabler — it uses a more accessible polymer formulation that reduces material cost relative to the high-temperature ceramic-filled systems used in HT grades.
When CML-11006 Is the Correct Choice
CML-11006 is appropriate for multi-layer designs where the operating temperature does not approach or exceed 90 °C continuously, the bus voltage is within the 10 kVAC breakdown headroom, and the design priority is cost-competitive production at volume. Practical applications include commercial variable-speed drive modules for HVAC systems (typically 240 VAC or 480 VAC input, ambient temperature 40–60 °C), LED driver electronics with moderate power density in temperature-controlled environments, multi-layer power supply designs for server and telecom infrastructure (48 VDC bus, controlled cabinet environment), and consumer power tools where cost pressure is real but thermal and voltage conditions are moderate.
The 10 lb/in peel strength is the key advantage of CML-11006 in multi-layer constructions. When multiple lamination press cycles are required — as they are in hybrid IMS + FR-4 stackups where the FR-4 sub-assembly is bonded to the IMS base in a second press cycle — the higher adhesion force reduces the risk of delamination at the dielectric-to-FR4 or dielectric-to-copper interface under thermal cycling. This makes CML-11006 one of the most fabrication-reliable grades for the hybrid stackup architecture.
Where CML-11006 Falls Short
CML-11006 should not be used in any design where continuous operating temperature approaches 90 °C. The 90 °C Tg means the dielectric begins transitioning from rigid to rubbery state at exactly the temperature that under-hood automotive designs, outdoor industrial inverters, and high-ambient LED fixtures routinely reach. Below the Tg, the dielectric is dimensionally stable and peel strength is reliable. Above the Tg, mechanical creep begins, solder joint stress increases, and long-term adhesion reliability degrades. The UL RTI of 130/130 °C describes a conservative long-term continuous rating well above Tg — but the Tg itself is the practical limit on intermittent peak temperature.
Table 3: CML-11006 vs MP-06503 vs HT-07006 for Multi-Layer Applications
Property
CML-11006
MP-06503
HT-07006
Intended Use
Cost-effective multi-layer
General purpose
High-temperature applications
Thermal Conductivity
1.1 W/m·K
1.0 W/m·K
2.2 W/m·K
Thermal Resistance
0.21 °C·in²/W
0.22 °C·in²/W
0.11 °C·in²/W
Dielectric Thickness
6 mil / 152 µm
6.5 mil / 165 µm
6 mil / 152 µm
Breakdown Voltage
10.0 kVAC
~3 kVAC typical
11.0 kVAC
Tg
90 °C
~130 °C
>150 °C
UL RTI (E/M)
130/130 °C
130/140 °C
140/140 °C
Peel Strength
10 lb/in (1.8 N/mm)
~6 lb/in
~6 lb/in
Multi-Layer Suitability
Best adhesion; temp-limited
Single-layer preferred
High-temp multi-layer
Relative Cost
Lowest in class
Low
Higher
Multi-Layer MCPCB Stackup Design Rules
Regardless of which Bergquist grade is selected, multi-layer metal core PCB design introduces fabrication and design rules that do not apply to single-layer boards. These are the constraints that separate a manufacturable multi-layer MCPCB specification from an incomplete one.
Via Isolation Through the Metal Layer
Standard plated-through-holes that penetrate the full stackup — including the metal substrate — must be electrically isolated from the base metal. The process (covered in detail in our metal core PCB manufacturing process article) involves drilling oversized pilot holes through the metal layer, filling them with insulating resin, curing, and re-drilling to the final via diameter before plating. Any via that contacts the metal substrate without this isolation creates a direct short from the circuit layer to the baseplate.
In hybrid IMS + FR-4 stackups, vias that connect only within the FR-4 portion of the board can be processed as standard plated-through-holes — they stop above the IMS dielectric and never encounter the metal base. Only vias that penetrate into or through the metal layer require isolation processing.
Blind Via Design for True Two-Layer IMS
True two-layer IMS boards avoid the via isolation problem entirely by using laser-drilled blind vias that connect the two copper circuit layers but stop at the IMS dielectric — never reaching the metal substrate. Laser drilling at 50–150 µm diameter is compatible with both HT-09009 and CML-11006 dielectric thicknesses. Copper-filled blind vias also serve a dual thermal function in these designs: they carry current between layers and they conduct heat from the second copper layer down toward the IMS dielectric.
Copper Weight Balancing in Multi-Layer MCPCB
In a multi-layer metal core PCB design, the copper weight on each circuit layer must be specified independently and balanced for both thermal and mechanical reasons. Asymmetric copper distribution — for example, 3 oz on the top power layer and 0.5 oz on a signal layer — creates CTE-driven stress that can warp the panel during lamination and cause solder joint reliability issues in the field. The general rule for multi-layer MCPCB is to keep copper weight symmetric across the stackup where possible, and to consult with the fabricator when asymmetric copper is unavoidable.
Solder Mask on Multi-Layer Boards with Thick Copper
As noted in our manufacturing process guide, solder mask application over thick copper (2–3 oz) in multi-layer MCPCB requires two-pass LPI application to achieve complete coverage at trace edges. This is even more important in multi-layer designs where the second copper layer may also carry power and use heavy copper. Specify this explicitly in your fabrication notes rather than leaving it to the fabricator’s standard process.
Application Matrix: Matching Grade to Multi-Layer Design Requirements
Table 4: Bergquist Grade Selection for Multi-Layer MCPCB Applications
When releasing a multi-layer metal core PCB design to fabrication, the following items represent the minimum required specification beyond standard single-layer MCPCB notes:
Stackup architecture — specify whether the design uses true multi-layer IMS, hybrid IMS + FR-4, or double-sided IMS. Each requires different DFM treatment and cannot be assumed from Gerber files alone. Via isolation strategy — explicitly call out which vias penetrate the metal layer and require resin fill isolation, and which vias are contained within the FR-4 layers. Blind via specification — if laser-drilled blind vias are used for two-layer IMS, confirm compatible with the IMS dielectric thickness and specify fill material (copper-filled preferred for thermal function). Copper weight per layer — state copper weight on each circuit layer independently. Solder mask specification — confirm two-pass LPI for any layer with 2 oz or heavier copper. Surface finish — ENIG specified for power and LED thermal pads; confirm ENIG nickel thickness (3–5 µm) and gold flash (0.05–0.1 µm). Hipot test voltage — state the dielectric test voltage that corresponds to your bus voltage × safety factor, and reference the specific dielectric grade. Dielectric brand and grade — specify by Bergquist grade designation (e.g., HT-09009 or CML-11006) rather than by conductivity number alone to prevent uncontrolled material substitution.
Useful Resources for Multi-Layer MCPCB Design
Resource
Description
Link
Bergquist Thermal Clad Selection Guide
Complete grade comparison including HT-09009 and CML-11006 properties table
Q1: What is the maximum number of copper layers practical on a multi-layer metal core PCB?
In production, two to four copper circuit layers above the IMS base is the practical maximum for most designs. Beyond four layers, the hybrid IMS + FR-4 approach becomes the only realistic fabrication method — the FR-4 sub-assembly is independently processed up to the required layer count, then bonded to the IMS base. Purely IMS-dielectric-only stacks beyond two layers are not standard production items and require custom engineering from the fabricator. The reason is via processing complexity: every additional layer above the IMS base that requires connection to lower layers must either use blind vias stopping at the IMS dielectric surface, or employ the resin-fill isolation process for each via that penetrates to the metal base. Each additional layer multiplies this complexity and cost. For most multi-layer MCPCB applications, the engineering-optimised answer is a two-copper-layer true IMS board or a two-to-four-layer hybrid IMS + FR-4, not a purely multi-layer IMS stack.
Q2: Can I substitute CML-11006 for MP-06503 in a multi-layer design to get higher breakdown voltage?
Yes, with care on the Tg. CML-11006 has a 10 kVAC breakdown voltage versus MP-06503’s approximately 3 kVAC — a significant improvement that makes CML-11006 genuinely better suited for bus voltages in the 240–480 VAC range. However, CML-11006’s Tg of 90 °C is lower than MP-06503’s approximately 130 °C. If your application involves operating temperatures above 85 °C — including self-heating from nearby components — CML-11006 will exceed its Tg under normal operation. MP-06503 remains the better choice in that temperature range. For applications where the operating temperature is reliably below 80 °C and the voltage isolation improvement matters, CML-11006 is the right substitution. The peel strength advantage of CML-11006 (10 vs 6 lb/in) is also a genuine fabrication benefit for multi-layer boards that go through additional press cycles.
Q3: How does CTE mismatch affect multi-layer MCPCB reliability, and which Bergquist grade is most tolerant?
CTE (coefficient of thermal expansion) mismatch is one of the primary reliability mechanisms in multi-layer MCPCB. The metal base expands at one rate (aluminium ~23 ppm/°C, copper ~17 ppm/°C), the dielectric at another, and the FR-4 layers at a third (~16–18 ppm/°C). Every thermal cycle stresses the interfaces between these layers. The via structures are particularly vulnerable: through-hole vias experience shear stress at the interface between the metal substrate and the surrounding dielectric during each thermal cycle, which is why copper-filled blind vias that stop above the metal are preferred over through-hole vias in thermally stressed applications. For grade selection, the HT grades (HT-09009, HT-07006) have higher Tg values that mean the dielectric remains in its rigid, dimensionally stable state over a wider operating range — which directly reduces CTE-driven stress at the interfaces. CML-11006’s 90 °C Tg means it transitions to the more thermally compliant rubbery state at temperatures that automotive and industrial power designs regularly reach, making it more prone to long-term fatigue at solder joints and via walls under thermal cycling.
Q4: HT-09009 has the same 2.2 W/m·K conductivity as HT-07006 but higher thermal resistance. Why, and how do I compensate?
The higher thermal resistance of HT-09009 (0.16 vs 0.11 °C·in²/W for HT-07006) is entirely caused by its greater dielectric thickness — 229 µm vs 152 µm. Thermal conductivity is a material bulk property; thermal resistance is the product of conductivity and geometry (R_θ = t / (k × A)). Both grades have the same ceramic-filled polymer composition at 2.2 W/m·K, but HT-09009 has 56% more thickness, which produces proportionally more thermal resistance. The compensation strategies available to a designer are: use copper base metal instead of aluminium to improve substrate-level heat spreading and partially offset the dielectric penalty; increase copper weight on the circuit layer from 1 oz to 2–3 oz to improve lateral spreading before heat enters the dielectric; reduce heatsink thermal resistance if the product architecture permits; and verify via junction temperature calculations with the 0.16 °C·in²/W value — not the 0.11 value of HT-07006 — to avoid an optimistic design that fails in the field.
Q5: Is it possible to mix Bergquist dielectric grades within a single multi-layer metal core PCB — for example, CML-11006 for signal layers and HT-09009 for power layers?
Mixing dielectric grades within a single board is technically possible in a hybrid IMS + FR-4 construction, where the IMS base uses one grade and the interlayer prepreg above it uses a different material. In practice, this is rarely done as a designed specification — the fabrication engineering overhead of tracking two different thermally conductive prepreg cure cycles in the same panel is significant, and the cost savings rarely justify it. The more common design approach is to select a single grade for the IMS dielectric layer based on the highest voltage and temperature requirement in the design (usually HT-09009 for high-voltage applications), accept the thermal resistance implications, and use standard FR-4 prepreg for the interlayer bonding in the hybrid stackup above it. The standard FR-4 interlayer does not see the component heat flux directly — that path goes through the IMS dielectric — so its lower thermal conductivity only matters for the signal layers, where power dissipation is minimal.
Summary: Choosing Between HT-09009 and CML-11006 for Multi-Layer MCPCB
HT-09009 and CML-11006 fill different positions in the Bergquist Thermal Clad product range and solve different problems in multi-layer metal core PCB design. HT-09009 is the grade for high-voltage power electronics — EV inverters, three-phase industrial drives, solar converters — where 20 kVAC breakdown headroom and 150 °C operation are non-negotiable. Its thermal resistance is the highest in the HT family, but the applications that need it accept that tradeoff because there is no alternative that delivers comparable voltage isolation at this power density.
CML-11006 is the grade for cost-optimised multi-layer designs in moderate-voltage, controlled-temperature environments — server power modules, HVAC drives, commercial power tools, and multi-layer LED driver boards where breakdown voltage matters more than it does on a 12–48 V LED board but the operating temperature stays well below 85 °C. Its exceptional peel strength makes it the most fabrication-reliable grade for hybrid multi-layer constructions that require multiple lamination cycles.
For both grades, the design decision workflow is the same: voltage isolation requirement first, then operating temperature, then thermal resistance, then cost. Getting that priority order right and selecting the grade accordingly is what separates a reliable multi-layer MCPCB from one that passes qualification but fails in the field.
For sourcing guidance and the complete Bergquist Thermal Clad product overview, visit the Bergquist PCB reference page.
Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.
Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.
Notes: For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.
