The XCKU060-2FFVA1156E is a high-performance field-programmable gate array (FPGA) from AMD Xilinx, belonging to the Kintex UltraScale family. Built on TSMC’s 20nm planar process technology, this device delivers an exceptional balance of signal processing bandwidth, logic density, and power efficiency — making it one of the most capable mid-range FPGAs available for demanding industrial, communications, and data center workloads.
If you are evaluating Xilinx FPGA solutions for your next design, the XCKU060-2FFVA1156E is a compelling choice worth examining in detail.
What Is the XCKU060-2FFVA1156E?
The XCKU060-2FFVA1156E is part of AMD’s Kintex UltraScale FPGA portfolio — a family engineered to deliver the highest signal processing bandwidth in a mid-range device. The part number breaks down as follows:
| Code Segment |
Meaning |
| XCKU060 |
Kintex UltraScale, 60-series device |
| -2 |
Speed grade: -2 (standard commercial speed) |
| FFVA |
Flip-chip fine-pitch ball grid array (FCBGA) package variant |
| 1156 |
1156-pin package |
| E |
Extended temperature or specific ordering suffix |
XCKU060-2FFVA1156E Key Specifications
Core Logic Resources
| Parameter |
Value |
| FPGA Family |
Kintex UltraScale |
| Process Technology |
20nm |
| Number of Logic Cells |
725,550 |
| Logic Blocks (CLBs) |
331,680 |
| Look-Up Tables (LUTs) |
331,680 |
| Flip-Flops |
663,360 |
Memory Resources
| Parameter |
Value |
| Block RAM (BRAM) |
38,000 Kbits (38 Mb) |
| Total RAM Bits |
38,912,000 bits |
| UltraRAM |
Not included (UltraScale+ feature) |
DSP and Processing
| Parameter |
Value |
| DSP Slices |
2,760 |
| Peak DSP Performance |
Up to 2,760 DSP operations/clock |
| MicroBlaze Soft Processor |
Supported (>200 DMIPs) |
I/O and Connectivity
| Parameter |
Value |
| User I/O Pins |
520 |
| Package / Case |
1156-BBGA, FCBGA |
| Total Package Pins |
1,156 |
| Transceivers (GTH) |
32 x 16.3 Gb/s GTH transceivers |
| PCIe |
Integrated PCIe Gen3 x8 block |
| Interlaken |
Supported |
| 100G Ethernet |
Supported |
Clocking
| Parameter |
Value |
| Clock Management |
MMCM, PLL |
| Clock Tiles |
Multiple CMT tiles |
| Max Frequency (Speed Grade -2) |
Up to 725 MHz (internal) |
Electrical and Thermal
| Parameter |
Value |
| Core Supply Voltage (VCCINT) |
0.922V – 0.979V (nominal 0.95V) |
| Operating Temperature |
0°C – 100°C (TJ) |
| Mounting Type |
Surface Mount |
| RoHS Compliant |
Yes (ROHS3) |
Package and Ordering
| Parameter |
Value |
| Package |
1156-FCBGA (Fine-pitch BGA) |
| Packaging |
Tray |
| Product Status |
Active |
| Manufacturer Lead Time |
~48 weeks (verify with distributor) |
| Manufacturer |
AMD (formerly Xilinx) |
| ECCN |
3A991.d |
| HTS Code |
8542390001 |
XCKU060-2FFVA1156E Architecture Overview
UltraScale Architecture Advantages
The XCKU060-2FFVA1156E is built on AMD’s UltraScale™ architecture, which was the first FPGA architecture to implement a true ASIC-like design methodology. Key architectural advantages include:
- Next-Generation SSI Technology — Stacked Silicon Interconnect (SSI) enables high bandwidth die-to-die connectivity, supporting designs that exceed single-die capacity.
- ASIC-Like Clocking — Eliminates clock skew through an advanced clock distribution network, improving timing closure.
- Cascade Interconnect — Reduces routing congestion and improves performance compared to prior-generation FPGA fabrics.
- Integrated Blocks — PCIe Gen3, 100G Ethernet MAC, Interlaken, and high-speed transceivers are hardened on-chip, freeing programmable logic for application-specific tasks.
GTH High-Speed Transceivers
The 32 GTH transceivers on the XCKU060 operate at up to 16.3 Gb/s each, making this device well-suited for high-bandwidth serial communication standards including:
- 10G/100G Ethernet
- PCIe Gen1/2/3
- Interlaken
- CPRI / OBSAI (wireless infrastructure)
- SATA / SAS
- Custom serial protocols
Supported Design Tools
The XCKU060-2FFVA1156E is fully supported by AMD’s Vivado Design Suite, which provides:
- RTL Synthesis — Optimized synthesis engine for UltraScale logic mapping
- Implementation — Placement and routing with timing-driven algorithms
- Simulation — Functional and timing simulation with third-party tool support
- IP Integrator — Block design environment for connecting IP cores
- Vitis HLS — High-level synthesis from C/C++ to FPGA logic
- Power Analysis — Xilinx Power Estimator (XPE) for pre-layout power budgeting
Minimum supported Vivado version for production silicon: Vivado Design Suite 2015.4 (v1.23)
Target Applications for the XCKU060-2FFVA1156E
Networking and Data Center
The XCKU060-2FFVA1156E is a natural fit for 100G packet processing pipelines. With hardened 100G Ethernet and Interlaken cores, plus 32 high-speed GTH transceivers, this device can handle line-rate processing for network appliances, network function virtualization (NFV), and data center switching.
Wireless Infrastructure
The device supports CPRI and OBSAI serial interfaces used in baseband unit (BBU) and remote radio head (RRH) designs. Its high DSP slice count (2,760 DSPs) enables intensive digital pre-distortion (DPD), beamforming, and signal processing workloads in heterogeneous wireless networks.
Medical Imaging
With support for high-bandwidth I/O and large on-chip memory, the XCKU060 is used in high-resolution medical imaging equipment including MRI reconstruction, CT scan processing, and ultrasound signal processing. The 8K4K video pipeline processing capability makes it equally useful in surgical and diagnostic display systems.
High-Performance Computing (HPC) and DSP
The 2,760 DSP48E2 slices support multiply-accumulate operations at extremely high throughput, enabling FFT engines, FIR filters, matrix multiplication accelerators, and radar/sonar signal processing. Paired with the large block RAM pool, this makes the XCKU060-2FFVA1156E a strong candidate for custom accelerator cards.
Test and Measurement
High I/O count (520 user I/Os), precision clocking (MMCM/PLL), and logic density make this device suitable for automated test equipment (ATE), protocol analyzers, and logic analyzers requiring deterministic timing and high parallel data capture rates.
XCKU060-2FFVA1156E vs. Other Kintex UltraScale Devices
| Device |
Logic Cells |
DSP Slices |
Block RAM (Kb) |
GTH Transceivers |
Package Options |
| XCKU025 |
326,400 |
1,152 |
21,875 |
20 |
FBVA676, SFVA784 |
| XCKU035 |
326,400 |
1,512 |
21,875 |
20 |
FBVA676, SFVA784 |
| XCKU060 |
725,550 |
2,760 |
38,000 |
32 |
FFVA1156, FFVA1517 |
| XCKU085 |
1,045,440 |
3,528 |
56,000 |
48 |
FFVA1517, FLVA1517 |
| XCKU115 |
1,451,520 |
5,520 |
75,900 |
64 |
FLVA1517, FLVB1760 |
The XCKU060 sits in the mid-range of the Kintex UltraScale family — providing approximately 2.2x the logic density of the XCKU035 while maintaining a manageable 1156-pin FCBGA footprint that is more board-design-friendly than the larger 1517-pin packages used on the XCKU085 and XCKU115.
PCB Design Considerations for the 1156-FCBGA Package
Board Stack-Up Recommendations
The 1156-FCBGA package used by the XCKU060-2FFVA1156E has a ball pitch of 1.0mm. PCB designers should consider the following:
- Minimum layer count: 10–14 layers recommended for power distribution and signal integrity
- Via technology: Microvias or blind vias recommended for inner BGA ball access
- Power planes: Separate VCCINT (0.95V), VCCAUX (1.8V), VCCO (variable) planes required
- Decoupling: Place 100nF and 10µF decoupling capacitors within 300mil of each power ball
- PCB material: Low-loss dielectric materials (e.g., Isola 370HR or equivalent) recommended for GTH transceiver signal paths
Thermal Management
The XCKU060 at -2 speed grade can dissipate significant power in high-utilization designs. Thermal management recommendations:
- Heatsink: Required for most applications exceeding moderate utilization
- TJ max: 100°C junction temperature (derate design for reliability headroom)
- Thermal interface material (TIM): Use low thermal resistance TIM between die lid and heatsink
- Airflow: Minimum 200 LFM airflow recommended in enclosed chassis
Compliance and Export Information
| Attribute |
Value |
| RoHS Status |
ROHS3 Compliant |
| Halogen Free |
Per manufacturer specifications |
| ECCN |
3A991.d |
| USHTS |
8542390001 |
| TARIC (EU) |
8542399000 |
| Warranty |
12 months from date of purchase |
| Cancellation / Return |
Non-Cancellable, Non-Returnable (NCNR) |
Important: The XCKU060-2FFVA1156E is classified under ECCN 3A991.d. Exporters must verify applicable export control regulations before shipping to restricted destinations.
Frequently Asked Questions
What is the difference between XCKU060 and XCKU060-2FFVA1156E?
XCKU060 refers to the base device die. The XCKU060-2FFVA1156E is the fully specified orderable part: the XCKU060 die, at -2 speed grade, in the FFVA (1156-pin FCBGA) package, with the “E” commercial suffix. Always use the full part number when ordering to ensure you receive the correct speed grade and package.
Is the XCKU060-2FFVA1156E compatible with Vivado HLS and Vitis?
Yes. The XCKU060 is fully supported in the Vivado Design Suite and Vitis unified software platform. Designs developed in Vitis HLS can be implemented on this device targeting C/C++ or OpenCL kernels.
What is the XCKU060 power consumption?
Power depends heavily on design utilization, clock frequency, and I/O activity. AMD’s Xilinx Power Estimator (XPE) tool should be used for accurate pre-layout power estimates. Typical static power is in the range of 2–4W; total dynamic power can range from 10W to 30W+ in high-utilization scenarios.
Can the XCKU060-2FFVA1156E be used in industrial temperature environments?
The -2FFVA1156E commercial suffix is rated for 0°C to 100°C junction temperature (TJ). For extended industrial temperature ranges, Xilinx offers XQKU060 (defense/aerospace) variants. Verify the specific temperature suffix for your operating environment requirements.
Summary
The XCKU060-2FFVA1156E is a powerful, production-proven mid-range FPGA that brings together 725,550 logic cells, 2,760 DSP slices, 38 Mb of block RAM, and 32 GTH high-speed transceivers in a manageable 1156-pin FCBGA package. Running at 0.95V core voltage with full Vivado tool support, it addresses a wide range of demanding applications — from 100G networking and DSP-intensive signal processing to medical imaging and wireless infrastructure.
Its combination of logic density, high-speed serial connectivity, and hardened IP blocks makes the XCKU060-2FFVA1156E a versatile choice for engineers requiring ASIC-class performance in a programmable, flexible platform.
