X5R Capacitor: A PCB Engineer’s Guide to General Purpose Ceramic Caps

Every board I design has X5R capacitors on it. Dozens of them, sometimes hundreds. They’re the bulk decoupling workhorses — the parts that fill out the power rail filtering, sit on every voltage regulator output, and provide the low-frequency energy storage that keeps digital ICs happy during load transients. Yet despite being the most commonly placed MLCC dielectric on modern PCBs, the X5R capacitor is also the most commonly misunderstood. I’ve watched engineers treat a 10 µF X5R like a guaranteed 10 µF, only to find 3 µF left after DC bias and temperature conspire against them. This guide is what I wish I’d had when I started designing boards.

What Is an X5R Capacitor?

An X5R capacitor is a multilayer ceramic capacitor (MLCC) built with a Class II ferroelectric dielectric — barium titanate (BaTiO₃) doped with various additives to achieve high volumetric efficiency. The “X5R” label isn’t a part number or a material name. It’s an EIA (Electronic Industries Alliance) classification code that tells you exactly three things about the part’s temperature behavior.

Code Character	Position	Meaning	X5R Value
X	1st — Minimum temperature	Lowest rated operating temperature	−55°C
5	2nd — Maximum temperature	Highest rated operating temperature	+85°C
R	3rd — Capacitance tolerance	Max capacitance change over temp range	±15%

In plain terms: the capacitance of an X5R part is guaranteed to stay within ±15% of the 25°C reference value anywhere from −55°C to +85°C. That ±15% window and the “R” suffix are identical to X7R. The only difference is the upper temperature limit — 85°C instead of 125°C. That 40-degree difference has significant implications for where you can and can’t use X5R, but it also comes with a meaningful advantage in capacitance density.

Why X5R Offers More Capacitance Per Square Millimeter

Because the X5R dielectric only needs to maintain its spec up to 85°C instead of 125°C, ceramic formulations can be optimized for higher permittivity at room temperature without worrying as much about behavior near the Curie point at elevated temperatures. The practical result: for the same package size and voltage rating, X5R MLCCs are available in higher capacitance values than X7R. Where X7R might top out at 10 µF in an 0805 package at 10V, X5R may offer 22 µF in the same footprint. This is exactly why X5R dominates in consumer electronics, mobile devices, and any design where board space is tight and operating temperatures stay moderate.

X5R Capacitor Key Specifications

Here’s a reference table covering the electrical parameters you’ll encounter when specifying X5R parts for a design.

Parameter	Typical Value / Range	Notes
Dielectric Class	EIA Class II	Ferroelectric (BaTiO₃ based)
Temperature Range	−55°C to +85°C	The “5” limits the upper end vs. X7R’s +125°C
Capacitance Change vs. Temp	±15% max	Referenced to 25°C; non-linear curve
Dielectric Constant (K)	3000–6000+	Higher than typical X7R formulations
Dissipation Factor (tan δ)	≤2.5% (≥50V); ≤12.5% (≤25V)	Higher DF at lower voltage ratings and larger cap values
Aging Rate	~2.5% per decade hour	Same as X7R; logarithmic, reversible with reflow
Available Capacitance Range	100 nF to 100 µF	Higher max than X7R for same package
Common Voltage Ratings	4V, 6.3V, 10V, 16V, 25V, 50V	Most commonly used at 6.3V–25V
Package Sizes	0201 through 2220	High-cap values mainly in 0805 and larger
Insulation Resistance	>10 GΩ or 500 MΩ·µF (whichever lower)	At rated voltage, 25°C

Understanding the EIA Dielectric Code System

The three-character system is straightforward once you see the lookup tables. Here’s the complete breakdown so you can decode any dielectric code you encounter on a BOM.

First character — Minimum temperature:

Code	Min Temp
X	−55°C
Y	−30°C
Z	+10°C

Second character — Maximum temperature:

Code	Max Temp
4	+65°C
5	+85°C
6	+105°C
7	+125°C
8	+150°C
9	+200°C

Third character — Capacitance change over the temp range:

Code	Max ΔC
R	±15%
S	±22%
T	+22% / −33%
U	+22% / −56%
V	+22% / −82%

That “V” at the bottom of the table is why Y5V capacitors are essentially unusable for anything that requires stable capacitance — an 82% loss is catastrophic. X5R’s ±15% “R” rating makes it a genuinely useful engineering part, not just a space filler.

The Real Problem: DC Bias Eats Your Capacitance

Temperature stability is what the EIA code promises. But in my experience, temperature is rarely the primary enemy of X5R capacitance on a real board. DC bias is.

When you apply a DC voltage across any Class II ceramic capacitor, the ferroelectric domains in the barium titanate dielectric begin to align and saturate. This directly reduces the effective permittivity, which means the capacitance drops. The effect is non-linear and depends heavily on how close the applied voltage is to the rated voltage and on how small the package is.

Here’s the part that catches people: X5R capacitors generally suffer worse DC bias effects than X7R for the same nominal capacitance and package size. The higher-K dielectric that gives X5R its volumetric advantage also makes it more voltage-sensitive.

X5R DC Bias Loss: Real-World Numbers

Based on published data from manufacturer simulation tools (Murata SimSurfing, TDK SEAT), here’s what typical X5R parts actually deliver under bias.

Part Description	Package	Voltage Rating	Applied DC Bias	Remaining Capacitance
4.7 µF X5R	0603	6.3V	3.3V	~2.1 µF (45%)
4.7 µF X5R	0603	6.3V	5V	~0.7 µF (15%)
10 µF X5R	0805	6.3V	3.3V	~5.8 µF (58%)
10 µF X5R	0805	10V	3.3V	~7.5 µF (75%)
22 µF X5R	1206	6.3V	3.3V	~11 µF (50%)
22 µF X5R	1210	10V	5V	~14 µF (64%)

The pattern is consistent: smaller packages lose more capacitance, and operating closer to rated voltage makes it dramatically worse. A 4.7 µF X5R cap at 80% of its rated voltage can deliver less than 1 µF. That’s not a defective part — that’s the physics of ferroelectric ceramics.

The practical rule I follow: For any X5R capacitor on a DC-biased rail, assume you’ll get 40–60% of nominal capacitance as a starting point. Then verify with the manufacturer’s simulation tool for the specific part number. If your circuit requires guaranteed minimum capacitance (like a switching regulator loop), design for the effective value — not the number on the reel label.

X5R vs. X7R vs. C0G: Picking the Right Dielectric

This is the decision that shapes your BOM more than almost any other component choice. Here’s a head-to-head comparison.

Characteristic	C0G (NP0)	X7R	X5R
Dielectric Class	Class I	Class II	Class II
Temperature Range	−55°C to +125°C	−55°C to +125°C	−55°C to +85°C
Cap Change vs. Temp	±0.3% (30 ppm/°C)	±15%	±15%
DC Bias Effect	Negligible	Moderate	Severe
Aging	None	~2.5%/decade hr	~2.5%/decade hr
Piezoelectric Noise	No	Yes	Yes
Max Capacitance (0805)	~10–22 nF	~10 µF	~22 µF
Volumetric Efficiency	Low	Medium	High
Cost per µF	High	Medium	Low
Best Application	Timing, RF, precision analog	General decoupling, automotive, industrial	Bulk decoupling, mobile, consumer, LED

When X5R Is the Right Choice

Low-voltage bulk decoupling (≤5V rails). On 1.0V, 1.2V, 1.8V, and 3.3V core and I/O rails, the DC bias effect is relatively mild because you’re operating far below the rated voltage. X5R gives you the most capacitance per unit area here, and that matters when you’ve got 50+ decoupling caps on a dense BGA layout.

Consumer electronics that run cool. Smartphones, tablets, wearables, smart home devices — these products rarely exceed 70°C at the PCB level. X5R is perfectly adequate and lets you hit your cost and size targets.

LED driver circuits. Output filtering for constant-current LED drivers typically operates at low voltage and moderate temperature. X5R bulk caps work well here.

Non-critical energy storage. Anywhere you need to soak up energy and release it, but the exact capacitance value isn’t tightly constrained — input bypass on USB ports, charge pump reservoirs, soft-start timing where tolerances are wide.

When X5R Is the Wrong Choice

Automotive under-hood or industrial environments. If ambient temperatures can exceed 85°C, the X5R spec is violated. Use X7R (rated to 125°C) or X8R (150°C) instead.

Switching regulator loops where stability is critical. Buck and boost converter compensation networks are sensitive to capacitance variation. The combined DC bias and temperature effects of X5R can push the effective capacitance far enough from the design target to cause instability. Use X7R with aggressive derating, or use the effective capacitance from the sim tool as your design value.

Oscillators, PLL loop filters, and precision timing. These need C0G. Period. No Class II dielectric — whether X5R or X7R — belongs in a circuit where capacitance stability directly determines frequency or phase accuracy.

Audio signal paths. Class II ceramics are piezoelectric. They convert mechanical vibration into electrical noise and AC voltage into audible buzz. Keep X5R and X7R out of the analog signal chain in audio equipment.

X5R Capacitor Aging: What It Means for Long-Life Products

Like all Class II MLCCs, X5R capacitors lose capacitance over time. The aging rate is typically quoted as 2.5% per decade hour — meaning the capacitance drops by 2.5% from hour 1 to hour 10, another 2.5% from hour 10 to hour 100, and so on logarithmically.

Over a 10-year product life, that works out to roughly 12–15% total capacitance loss from aging alone. Combined with DC bias and temperature effects, your worst-case effective capacitance can be significantly lower than the nominal value.

The good news: aging is fully reversible. Heating the capacitor above its Curie point (approximately 125°C for BaTiO₃-based formulations) resets the crystalline structure and restores the original capacitance. The reflow soldering process does this automatically. So after your board comes out of the oven, the aging clock starts fresh from zero.

Design tip for long-life products: If your product must last 10+ years (industrial controls, medical devices, telecom infrastructure), add a 15–20% aging margin on top of your DC bias derating. For a 10 µF X5R cap on a 3.3V rail, your effective long-term capacitance might be only 4–5 µF once you stack DC bias loss and aging together.

Handling and Reliability Considerations

Flex Cracking

MLCCs are ceramic. Ceramics are brittle. When the PCB flexes — during depaneling, press-fit connector insertion, screw-down mounting, or even thermal cycling — the ceramic body can crack. Larger packages are more susceptible because they span more board area and experience greater strain.

For X5R parts in 1206 and larger packages placed near board edges, mounting holes, or panel break-away tabs, consider specifying flexible termination (“soft term”) variants. These use a conductive polymer layer between the ceramic body and the tin termination that absorbs mechanical stress. It adds a small cost premium but prevents the intermittent shorts and field failures that hairline flex cracks cause.

Tombstoning and Component Placement

Small X5R capacitors (0201, 0402) are prone to tombstoning during reflow if the solder paste deposit or pad design is asymmetric. Follow your paste manufacturer’s recommended stencil aperture design for these packages, and ensure thermal symmetry between the two pads by avoiding one pad connected to a large copper pour while the other connects to a thin trace.

Useful Resources for X5R Capacitor Selection

Resource	Description	Link
Murata SimSurfing	Free online tool: plot capacitance vs. DC bias, temperature, frequency, and impedance for specific part numbers	ds.murata.co.jp/simsurfing
TDK SEAT Tool	TDK’s equivalent simulation tool for MLCC DC bias and frequency analysis	product.tdk.com
KEMET K-SIM	KEMET’s online MLCC simulation and part selection tool	ksim.kemet.com
Analog Devices Tech Article	Classic article explaining why your 4.7 µF cap becomes 0.33 µF under DC bias	analog.com
Johanson Dielectrics — Aging Note	Clear explanation of MLCC aging mechanics with charts	johansondielectrics.com
PCBSync — Capacitor Knowledge Base	Comprehensive overview of capacitor types and selection guidance	pcbsync.com/capacitor

Frequently Asked Questions About X5R Capacitors

Can I use an X5R capacitor in place of an X7R?

Only if your operating temperature stays below 85°C. The electrical behavior (capacitance range, aging rate, piezoelectric effects) is essentially the same between X5R and X7R — the only guaranteed difference is the upper temperature limit. However, X5R typically has worse DC bias characteristics than X7R for the same capacitance and package, because the higher-K dielectric formulation that enables greater volumetric efficiency also amplifies voltage sensitivity. If you’re substituting X5R for X7R on a power rail, re-check the effective capacitance under your operating voltage using a simulation tool.

How bad is the DC bias effect on X5R capacitors, really?

It can be severe. An X5R capacitor operating at 50% of its rated voltage typically retains only 50–70% of nominal capacitance. At 80% of rated voltage, expect 30–40% remaining. Combined with temperature drift at 85°C, a nominal “10 µF” X5R part might deliver only 3 µF in the worst case. This is the single most important factor to account for when designing with X5R parts, especially on power supply outputs and inputs where loop stability depends on actual capacitance.

What’s the difference between X5R and Y5V capacitors?

Both are Class II ceramics, but Y5V allows capacitance to drop by up to 82% over its temperature range (+10°C to +85°C), while X5R limits the variation to ±15% over a wider range (−55°C to +85°C). Y5V achieves higher capacitance per volume because its dielectric constant is much higher (up to 25,000 vs. 3000–6000 for X5R), but the instability makes it unsuitable for any application where capacitance accuracy matters. Y5V is really only acceptable for circuits operating near room temperature where the exact capacitance value isn’t critical.

Does the aging of X5R capacitors affect my measurement during incoming inspection?

Yes, and this confuses quality teams regularly. If an X5R reel has been sitting in storage for a year or more, the capacitance will have drifted lower due to aging. A part with a nominal value of 10 µF ±10% might measure at 9.0 µF or even 8.5 µF — which looks like it’s out of spec. But manufacturers set their test limits so that parts are within tolerance at 1,000 hours after last heat. After reflow soldering, the Curie point is exceeded and aging resets, bringing the capacitance back to its initial value. Don’t reject parts based on pre-reflow measurements unless you’ve de-aged them first (30 minutes at 150°C is sufficient).

Should I use one large X5R capacitor or several smaller ones in parallel?

Several smaller ones, almost always. Paralleling multiple MLCCs gives you lower ESR and ESL (better high-frequency performance), distributes mechanical stress across more solder joints (better flex crack resilience), and reduces the DC bias effect on each individual part because each cap carries a smaller fraction of the total stored energy. For example, two 10 µF X5R caps in 0805 packages will generally deliver more effective capacitance under bias than one 22 µF X5R in a 1210 — and they’ll have lower impedance at high frequencies due to the parallel ESL reduction. The downside is more placement positions, which costs board area and pick-and-place time. But for production boards where reliability matters, the parallel approach wins.

The Bottom Line

The X5R capacitor is the right part for the right job — and that job is bulk capacitance in moderate-temperature, low-to-mid voltage environments where board space is at a premium. It gives you more microfarads per square millimeter than any other stable ceramic dielectric, and at lower cost. But “general purpose” doesn’t mean “use without thinking.” Account for DC bias derating, respect the 85°C temperature ceiling, factor in aging for long-life products, and always verify effective capacitance with the manufacturer’s simulation tools before you finalize your BOM. The number printed on the reel is where the engineering starts — not where it ends.