The XC2S200-6FGG1090C is a high-performance Field-Programmable Gate Array (FPGA) from Xilinx’s Spartan-II family. Designed for cost-sensitive, high-volume applications, this device delivers 200,000 system gates, 5,292 logic cells, and an advanced Fine-Pitch Ball Grid Array (FBGA) package — making it a reliable choice for engineers seeking a powerful, programmable logic solution without the overhead of custom ASICs. Whether you are designing communication systems, embedded controllers, or digital signal processing modules, the XC2S200-6FGG1090C offers the flexibility and density to meet modern design demands.
What Is the XC2S200-6FGG1090C?
The XC2S200-6FGG1090C belongs to Xilinx’s Spartan-II FPGA family, a series of programmable logic devices built on a 0.18µm process technology. The part number breaks down as follows:
- XC2S200 – Xilinx Spartan-II device with 200K system gates
- -6 – Speed grade 6 (fastest available in the commercial range)
- FGG – Fine-Pitch Ball Grid Array (BGA) package, Pb-free variant
- 1090 – Package pin count (1,090 balls)
- C – Commercial temperature range (0°C to +85°C)
This FPGA is an ideal drop-in solution for engineers looking to replace mask-programmed ASICs with a fully reconfigurable, in-field-updateable alternative.
For a broader overview of the Xilinx Spartan-II product lineup, visit Xilinx FPGA.
XC2S200-6FGG1090C Key Specifications
General Device Parameters
| Parameter |
Value |
| Manufacturer |
Xilinx (AMD) |
| Product Family |
Spartan-II |
| Part Number |
XC2S200-6FGG1090C |
| Number of System Gates |
200,000 |
| Logic Cells |
5,292 |
| CLB Array |
28 × 42 |
| Total CLBs |
1,176 |
| Maximum User I/O |
284 |
| Process Technology |
0.18µm |
| Core Voltage (VCCINT) |
2.5V |
| Speed Grade |
-6 (Commercial only) |
| Temperature Range |
0°C to +85°C (Commercial) |
Memory Resources
| Memory Type |
Capacity |
| Distributed RAM |
75,264 bits |
| Block RAM |
56K bits |
| Total On-Chip RAM |
~131K bits |
Package Information
| Parameter |
Value |
| Package Type |
Fine-Pitch Ball Grid Array (FBGA) |
| Package Code |
FGG |
| Pin / Ball Count |
1,090 |
| Pb-Free (RoHS) |
Yes (G suffix) |
| Mounting Type |
Surface Mount |
XC2S200-6FGG1090C Architecture Overview
Configurable Logic Blocks (CLBs)
The XC2S200-6FGG1090C features 1,176 Configurable Logic Blocks arranged in a 28×42 array. Each CLB contains four logic cells, with each logic cell consisting of two function generators (look-up tables), two storage elements (flip-flops or latches), and dedicated carry and control logic. This architecture supports a wide range of combinational and sequential logic implementations.
Block RAM
The device includes 56K bits of on-chip Block RAM, organized into dedicated dual-port memory blocks located in two columns on opposite sides of the die. These memory resources are ideal for implementing FIFOs, buffers, and local data storage without consuming general-purpose CLB resources.
Delay-Locked Loops (DLLs)
Four on-chip Delay-Locked Loops (DLLs) — one at each corner of the die — provide zero-delay clock buffering, clock multiplication/division, and phase shifting. This eliminates clock skew across the device and allows designers to implement high-speed, synchronous systems with precision timing.
Input/Output Blocks (IOBs)
The XC2S200-6FGG1090C provides up to 284 user I/O pins, each supported by configurable Input/Output Blocks. The IOBs support a variety of I/O standards and include programmable pull-up, pull-down, and keeper circuits.
Spartan-II Family Comparison Table
| Device |
System Gates |
Logic Cells |
CLB Array |
Max User I/O |
Dist. RAM (bits) |
Block RAM |
| XC2S15 |
15,000 |
432 |
8×12 |
86 |
6,144 |
16K |
| XC2S30 |
30,000 |
972 |
12×18 |
92 |
13,824 |
24K |
| XC2S50 |
50,000 |
1,728 |
16×24 |
176 |
24,576 |
32K |
| XC2S100 |
100,000 |
2,700 |
20×30 |
176 |
38,400 |
40K |
| XC2S150 |
150,000 |
3,888 |
24×36 |
260 |
55,296 |
48K |
| XC2S200 |
200,000 |
5,292 |
28×42 |
284 |
75,264 |
56K |
The XC2S200 is the largest and highest-density device in the Spartan-II family, offering the most logic resources, memory, and I/O options.
Top Features of the XC2S200-6FGG1090C
High-Performance Speed Grade
The -6 speed grade is the fastest speed grade available in the Spartan-II commercial range, delivering maximum operating frequency up to 263 MHz. This makes the XC2S200-6FGG1090C well-suited for demanding, high-throughput applications.
Reconfigurability and In-Field Updates
Unlike fixed-function ASICs or standard logic ICs, the XC2S200-6FGG1090C can be reprogrammed in the field without hardware replacement. Design upgrades, bug fixes, and feature additions can be deployed via configuration updates — dramatically reducing time-to-market and long-term maintenance costs.
Pb-Free (RoHS Compliant) Packaging
The “G” suffix in FGG indicates a Pb-free package, ensuring compliance with RoHS environmental directives. This makes the XC2S200-6FGG1090C suitable for use in environmentally regulated markets worldwide.
Low-Cost ASIC Alternative
The Spartan-II family was engineered as a cost-effective, high-volume alternative to mask-programmed ASICs. It eliminates NRE (Non-Recurring Engineering) costs, lengthy development cycles, and the risk of costly design respins associated with traditional custom silicon.
XC2S200-6FGG1090C Applications
The XC2S200-6FGG1090C is well-suited for a broad range of applications across multiple industries:
Embedded Systems and Control
Its rich logic resources and I/O flexibility make this FPGA ideal for implementing embedded microcontroller cores, custom state machines, and real-time control systems in industrial and automotive applications.
Digital Signal Processing (DSP)
The combination of distributed RAM, block RAM, and high-speed logic cells supports efficient implementation of DSP algorithms including filters, FFTs, convolution, and data encoding/decoding.
Communications and Networking
With up to 284 user I/O pins and fast DLL-based clocking, the XC2S200-6FGG1090C is widely used in serial and parallel communication interfaces, protocol bridges, line cards, and network switches.
Test and Measurement Equipment
The device’s reconfigurability makes it valuable in test instrumentation, where design flexibility and rapid prototyping are essential.
Prototyping and ASIC Emulation
Engineers routinely use the XC2S200-6FGG1090C as a prototyping platform to validate ASIC designs before tape-out, shortening development risk and time.
Configuration and Design Tools
Supported Configuration Modes
The XC2S200-6FGG1090C supports multiple configuration modes for loading the bitstream into the device:
| Configuration Mode |
Description |
| Master Serial |
FPGA controls configuration from external serial PROM |
| Slave Serial |
External controller drives serial configuration |
| Slave Parallel (SelectMAP) |
Parallel 8-bit configuration interface |
| JTAG (Boundary Scan) |
IEEE 1149.1 compliant configuration and debug |
Recommended Design Tools
| Tool |
Description |
| Xilinx ISE Design Suite |
Primary synthesis, place-and-route, and bitstream generation for Spartan-II |
| ModelSim / ISIM |
HDL simulation (VHDL / Verilog) |
| ChipScope Pro |
In-circuit debugging and signal analysis |
| IMPACT / iMPACT |
Configuration file download and JTAG programming |
Note: The Spartan-II family is supported in Xilinx ISE (not Vivado). ISE Design Suite is the recommended toolchain for XC2S200-6FGG1090C development.
XC2S200-6FGG1090C Ordering and Part Number Decoder
Understanding the Xilinx part number format helps ensure you order the correct variant:
| Field |
Code |
Meaning |
| Device Family |
XC2S |
Xilinx Spartan-II |
| Gate Count |
200 |
200K system gates |
| Speed Grade |
-6 |
Fastest commercial grade |
| Package Type |
FGG |
Fine-Pitch BGA, Pb-free |
| Pin Count |
1090 |
1,090 ball count |
| Temperature Range |
C |
Commercial (0°C to +85°C) |
Frequently Asked Questions (FAQ)
What is the difference between XC2S200-6FGG1090C and XC2S200-5FGG1090C?
The key difference is the speed grade. The -6 variant offers faster propagation delays and a higher maximum operating frequency than the -5 variant. Speed grade -6 is exclusively available in the commercial temperature range.
Is the XC2S200-6FGG1090C RoHS compliant?
Yes. The “G” in FGG denotes a Pb-free package, making this part RoHS compliant and suitable for use in environmentally regulated products.
What software do I need to program the XC2S200-6FGG1090C?
Xilinx ISE Design Suite is the correct toolchain for the Spartan-II family. Vivado does not support this older device family. Use HDL (VHDL or Verilog) for design entry and iMPACT for JTAG-based configuration.
Can this FPGA replace an ASIC?
Yes. The XC2S200-6FGG1090C is designed as a programmable ASIC alternative. It eliminates mask costs and allows in-field updates, making it a lower-risk option at low-to-medium production volumes.
What is the core supply voltage?
The VCCINT core supply is 2.5V. I/O supply (VCCO) voltage is configurable per bank to support multiple I/O standards.
Summary: Why Choose the XC2S200-6FGG1090C?
The XC2S200-6FGG1090C delivers the highest logic density in the Spartan-II family combined with the fastest commercial speed grade, Pb-free packaging, and a large 1,090-ball BGA footprint that maximizes I/O flexibility. It is a proven, reliable solution for engineers who need a cost-effective, reconfigurable logic device for communications, DSP, embedded control, and prototyping applications.
With 200K system gates, 5,292 logic cells, 131K bits of total on-chip RAM, four DLLs, and up to 284 user I/Os, the XC2S200-6FGG1090C remains one of the most capable devices in the classic Spartan-II portfolio.
