Quartus Prime Software: Download, Installation & Tutorial Guide (All Versions)

If you’ve spent any time working with Intel or Altera FPGAs and CPLDs, you know that Quartus Prime (formerly Altera Quartus) is the backbone of the entire development workflow. I’ve been using this software since the Quartus II days, and while the branding has changed several times—from Altera to Intel and now back to Altera—the core functionality remains essential for anyone designing with programmable logic devices.

This comprehensive guide covers everything you need to know about Intel Quartus software, from downloading the right version for your hardware to navigating the installation process and getting your first design compiled. Whether you’re working with legacy Quartus 13.1 projects, modern Quartus Prime 20.1 designs, or somewhere in between, you’ll find practical guidance here.

What is Quartus Prime Software?

Quartus Prime is a multiplatform integrated development environment (IDE) for designing, compiling, and programming Intel (formerly Altera) FPGAs, CPLDs, and SoCs. The software handles everything from design entry through synthesis, place-and-route, timing analysis, and device programming.

The tool supports multiple design entry methods including VHDL, Verilog, SystemVerilog, and schematic capture. For those of us who’ve worked with both Xilinx Vivado and Intel Quartus, the workflows are conceptually similar, though the interface details differ significantly.

Key Features of Quartus Prime

The software includes several critical components for FPGA development:

• Synthesis Engine: Converts HDL code to gate-level netlists optimized for target devices
• Fitter: Performs placement and routing within the FPGA fabric
• Timing Analyzer: Validates timing constraints using industry-standard SDC format
• Platform Designer (Qsys): System integration tool for connecting IP cores
• Signal Tap Logic Analyzer: On-chip debugging without external equipment
• Programmer: Downloads configurations to target hardware via USB-Blaster or JTAG

Quartus Prime Editions: Lite, Standard, and Pro Compared

One of the first decisions you’ll face is choosing which edition to install. Intel offers three distinct versions, each targeting different device families and feature requirements.

Feature	Quartus Prime Lite	Quartus Prime Standard	Quartus Prime Pro
Price	Free	Paid Subscription	Paid Subscription
License Required	No	Yes	Yes
MAX II/V CPLDs	✓	✓	—
MAX 10 FPGAs	✓	✓	—
Cyclone IV/V	✓	✓	—
Cyclone 10 LP	✓	✓	—
Cyclone 10 GX	—	—	✓ (Free)
Arria II	Limited	✓	—
Arria V/10	—	✓	✓
Stratix IV/V	—	✓	—
Stratix 10	—	—	✓
Agilex	—	—	✓
Partial Reconfiguration	—	Optional	✓
Design Partitioning	—	✓	✓
Register Retiming	—	✓	✓

When to Use Quartus Prime Lite Edition

For hobbyists, students, and engineers working with cost-optimized devices, Quartus Prime Lite is often sufficient. The free edition supports:

• MAX II and MAX V CPLD Quartus development
• MAX 10 FPGA designs
• Cyclone IV GX/E devices
• Cyclone V devices
• Cyclone 10 LP devices

The main limitations involve advanced optimization features and support for high-end device families. If you’re designing with Cyclone or MAX devices for production, Lite edition can handle most requirements without licensing costs.

Understanding Quartus Price and Licensing

The Quartus price varies significantly based on your needs. Here’s the general breakdown:

License Type	Approximate Cost	Notes
Quartus Prime Lite	Free	No license file required
Quartus Prime Standard	~$2,995/year	Subscription model
Quartus Prime Pro	~$3,995/year	Required for Stratix 10, Agilex
Node-locked vs Floating	Varies	Floating licenses cost more

For many PCB engineers like myself, the Lite edition covers 90% of what we need. I only reach for Standard when a client specifically requires Arria or Stratix devices.

Downloading Quartus Prime Software

Current Versions Download Links

Intel maintains the official download center at their FPGA software portal. Here are direct paths to the most commonly needed versions:

Latest Stable Releases:

• Quartus Prime Pro Edition 25.x: Intel FPGA Download Center
• Quartus Prime Standard Edition 23.x
• Quartus Prime Lite Edition 23.x

Recommended Legacy Versions:

• Quartus Prime 20.1: Last version with ModelSim-Intel FPGA Edition (before Questa transition)
• Quartus Prime 18.1: Stable release with broad device support
• Quartus Prime 17.0: Good for Cyclone IV/V and MAX 10 development

Legacy Quartus II Version Availability

Finding older Altera Quartus versions has become challenging since Intel deprecated many downloads in March 2020. Here’s what’s currently available:

Version	Status	Supported Devices
Quartus 13.1	Archived but available	Cyclone II/III/IV/V, MAX II
Quartus 13.0 SP1	Still downloadable	Cyclone II/III/IV/V
Quartus 12	Discontinued	SOPC Builder support
Quartus 9.1	Discontinued	Cyclone I/II/III
Quartus 15.0	Limited availability	MAX 10, Cyclone IV/V

For Quartus 13.1 and earlier versions supporting legacy devices like Cyclone II, check the archived downloads section or contact your Intel FAE. The Internet Archive has preserved some versions for educational purposes.

Download Process Step-by-Step

1. Navigate to Intel FPGA Software Downloads
2. Select your desired edition (Lite, Standard, or Pro)
3. Choose your operating system (Windows or Linux)
4. Select download method:
   1. Web Installer: Smaller initial download, fetches components as needed
   1. Complete Download: Single large file (~15-25GB depending on edition)
   1. Individual Files: Download only specific components
5. Create or sign into your Intel account
6. Accept license agreements and begin download

For Quartus Prime 18.1 and Quartus Prime 20.1, I recommend the complete download option if you have stable internet. The web installer can be frustrating on slower connections.

Installing Quartus Prime on Windows

System Requirements

Before installation, verify your system meets these requirements:

Component	Minimum	Recommended
OS	Windows 10 64-bit	Windows 10/11 64-bit
RAM	8 GB	32 GB or more
Disk Space	30 GB	100+ GB (with device support)
Display	1024×768	1920×1080 or higher
Processor	Intel/AMD 64-bit	Multi-core recommended

Windows Installation Steps

1. Extract the installer if downloaded as a compressed archive
2. Run setup.bat or the main executable as Administrator
3. Accept the license agreement
4. Select installation directory: Avoid paths with spaces (e.g., use C:\intelFPGA\23.1 not C:\Program Files\Intel FPGA)
5. Choose components:
   1. Quartus Prime (required)
   1. Device support files for your target FPGAs
   1. ModelSim or Questa simulator (highly recommended)
   1. Nios II EDS if developing embedded systems
6. Allow sufficient disk space (verify before proceeding)
7. Complete installation and install USB-Blaster drivers when prompted

Installing Device Support Separately

If you selected a minimal installation, you can add device support later:

1. Open Quartus Prime
2. Go to Tools → Install Devices
3. Select device families to add
4. Follow the device installer wizard

This approach saves disk space by installing only what you need for current projects.

Installing Quartus Prime on Linux

Linux Distribution Support

Intel officially supports:

• Red Hat Enterprise Linux 7/8
• CentOS 7/8
• Ubuntu 18.04/20.04/22.04
• SUSE Linux Enterprise 12/15

For Arch Linux users, the AUR provides packages like quartus-free that handle dependencies automatically.

Required Dependencies

Before installing on Ubuntu/Debian systems, install these 32-bit libraries:

sudo dpkg –add-architecture i386

sudo apt update

sudo apt install libc6:i386 libncurses5:i386 libstdc++6:i386 \

    libxft2:i386 libxext6:i386 lib32z1 libpng12-0

Linux Installation Process

1. Make the installer executable:

chmod +x QuartusLiteSetup-*.run

1. Run the installer:

./QuartusLiteSetup-*.run

Follow the graphical installer prompts

Add Quartus to your PATH by editing ~/.bashrc:

export PATH=$PATH:/path/to/intelFPGA_lite/23.1/quartus/bin

export QUARTUS_ROOTDIR=/path/to/intelFPGA_lite/23.1/quartus

1. Configure USB-Blaster permissions by creating a udev rule:

sudo nano /etc/udev/rules.d/51-altera-usb-blaster.rules

Add:

SUBSYSTEM==”usb”, ATTR{idVendor}==”09fb”, ATTR{idProduct}==”6001″, MODE=”0666″

SUBSYSTEM==”usb”, ATTR{idVendor}==”09fb”, ATTR{idProduct}==”6010″, MODE=”0666″

1. Reload udev rules:

sudo udevadm control –reload-rules

ModelSim Quartus Integration and Questa Setup

Understanding Simulation Tool Options

The simulation landscape for Intel FPGA development has evolved significantly:

Tool	Versions	License	Notes
ModelSim-Altera	Pre-2020	Free Starter Edition	Legacy but still functional
ModelSim-Intel FPGA	Up to 20.1	Free Starter Edition	Replaced by Questa
Intel FPGA ModelSim	20.1.1	Free/Paid	Final ModelSim release
Questa-Intel FPGA	21.1+	Free (requires license file)	Current standard
Questa-Altera FPGA	25.x+	Free Starter Edition	Post-spinoff branding

Setting Up ModelSim Quartus Integration

For Quartus Prime 18.1 and earlier with Altera ModelSim:

1. During Quartus installation, ensure ModelSim-Intel FPGA Starter Edition is selected
2. After installation, configure the path in Quartus:
   1. Go to Tools → Options → EDA Tool Options
   1. Set ModelSim-Altera path to: C:\intelFPGA\18.1\modelsim_ase\win32aloem
3. Verify integration by creating a simple testbench and running Tools → Run Simulation Tool → RTL Simulation

Configuring Questa for Quartus Prime 21.1+

The transition from ModelSim Quartus to Questa requires obtaining a free license:

1. Visit the Intel Self-Service Licensing Center
2. Register for an account if needed
3. Select “Evaluation or Free Licenses”
4. Choose “Questa-Intel FPGA Starter Edition”
5. Generate a license file tied to your NIC ID (MAC address)
6. Save the license file to your Quartus installation directory
7. Set the LM_LICENSE_FILE environment variable to point to your license

Questa offers up to 2.5x faster Verilog simulation performance compared to ModelSim, making the migration worthwhile for larger designs.

Getting Started: Your First Quartus Project

Creating a New Project

Let’s walk through creating a basic CPLD Quartus or FPGA project:

1. Launch Quartus Prime
2. Select File → New Project Wizard
3. Set the project directory and name (avoid spaces in paths)
4. Skip the “Add Files” step for now
5. Select your target device:
   1. Choose the device family (e.g., MAX 10, Cyclone V)
   1. Filter by package type if known
   1. Select your specific part number
6. Configure EDA tool settings (typically defaults are fine)
7. Click Finish

Writing Your First Verilog Module

Create a simple LED blink design to verify your toolchain:

module led_blink (

    input wire clk,        // 50MHz clock input

    output reg led         // LED output

);

    reg [24:0] counter;    // 25-bit counter for ~0.67s period

    always @(posedge clk) begin

        counter <= counter + 1’b1;

        if (counter == 25’d0)

            led <= ~led;

    end

endmodule

Pin Assignment

Before compilation, assign your I/O pins:

1. Open Assignments → Pin Planner
2. For each signal, double-click the Location column
3. Enter the pin number matching your development board schematic
4. Set appropriate I/O standards (typically LVCMOS 3.3V for most dev boards)

Compilation and Programming

1. Click Processing → Start Compilation or press Ctrl+L
2. Review the compilation report for warnings and errors
3. Connect your USB-Blaster programmer
4. Open Tools → Programmer
5. Click Hardware Setup and select your USB-Blaster
6. Add your .sof file if not auto-detected
7. Check Program/Configure checkbox
8. Click Start

Read more about Altera articles:

Working with Nios II EDS and Embedded Development

What is Nios II EDS?

The Nios II Embedded Design Suite provides tools for developing software on Intel’s soft-core processor. Key components include:

• Eclipse-based IDE for C/C++ development
• BSP (Board Support Package) editor
• GCC-based compiler toolchain
• Debugging and profiling tools

Note: Intel announced Nios II discontinuation in 2023, with Nios V (RISC-V based) as the successor. However, Nios2EDS remains important for maintaining existing designs.

Installing Eclipse IDE for Nios II

Starting with Quartus 19.1, Eclipse IDE requires manual installation:

1. Download Eclipse CDT 8.8.1 (Mars.2) from Eclipse archives
2. Extract to a folder named eclipse_nios2
3. Navigate to <quartus_path>/nios2eds/bin/
4. Extract eclipse_nios2_plugins.zip to your Eclipse folder
5. Copy the configured Eclipse folder to <quartus_path>/nios2eds/bin/eclipse_nios2

Creating a Nios II System with Platform Designer

1. Open Tools → Platform Designer (formerly Qsys)
2. Add a clock source component
3. Add Nios II processor (select appropriate variant)
4. Add on-chip memory for program storage
5. Add JTAG UART for console output
6. Connect clock and reset signals
7. Assign base addresses
8. Generate HDL output
9. Instantiate the generated system in your top-level design

Quartus Version History and Device Support Matrix

Understanding which Quartus version supports your hardware is crucial for legacy projects:

Quartus Version	Release Year	Key Device Support	Notes
Quartus 9.1	2009	Cyclone I/II/III, Stratix II	Last 32-bit support
Quartus 11.0	2011	Cyclone IV, Arria II	SOPC Builder included
Quartus 12	2012	Cyclone V, MAX V	Last SOPC Builder version
Quartus 13.1	2013	All 28nm devices	Last Cyclone II support
Quartus 15	2015	MAX 10 introduced	Qsys replaces SOPC Builder
Quartus 17.0	2017	Cyclone 10 LP	Last 32-bit Windows
Quartus Prime 18.1	2018	Stratix 10	Stable long-term release
Quartus Prime 20.1	2020	Agilex	Last ModelSim version
Quartus Prime 21.x+	2021+	Latest devices	Questa simulator

Useful Resources and Download Links

Official Intel/Altera Resources

Resource	URL	Description
FPGA Software Download Center	intel.com/fpga/downloads	Current and archived versions
Documentation Portal	intel.com/fpga/docs	User guides and handbooks
Self-Service Licensing	intel.com/fpga-sslc	License file generation
Altera Community Forums	community.altera.com	Peer support and discussions

Third-Party Resources

Resource	Description
FPGA Academy	University tutorials and example designs
Terasic	Development board documentation and reference designs
OpenCores	Open-source IP cores compatible with Quartus
Intel FPGA YouTube	Official video tutorials

Archived Software Sources

For discontinued versions like Quartus 9.1 or Quartus 12, consider:

• Internet Archive (archive.org) – Educational preservation
• University mirrors – Check your institution’s software portal
• Intel FAE request – For legitimate production needs

Troubleshooting Common Issues

License Errors

Problem: “License file not found” or validation errors

Solutions:

1. Verify LM_LICENSE_FILE environment variable
2. Check license file matches your NIC ID
3. Ensure firewall allows FlexLM communication
4. For Questa, confirm you obtained the correct license type

USB-Blaster Not Detected

Problem: Programmer cannot find hardware

Solutions:

1. Reinstall USB-Blaster drivers from <quartus>/drivers/usb-blaster
2. On Linux, verify udev rules are correctly configured
3. Try a different USB port (preferably USB 2.0)
4. Check Device Manager for driver conflicts

Compilation Failures

Problem: Design fails timing or resource constraints

Solutions:

1. Review the Compilation Report for specific failures
2. Use Timing Analyzer to identify critical paths
3. Consider Design Space Explorer for optimization
4. Verify pin assignments don’t conflict with dedicated pins

Frequently Asked Questions (FAQs)

Is Quartus Prime Lite free for commercial use?

Yes, Quartus Prime Lite Edition is completely free for both personal and commercial use. There are no licensing restrictions on products developed using the Lite edition. The main limitations involve device support (no Stratix, limited Arria) and absence of some advanced optimization features.

Can I use Quartus Online without installing software?

Intel does not currently offer a full Quartus Online cloud-based development environment. However, you can use:

• Intel DevCloud for oneAPI FPGA development
• CPUlator (web-based Nios II simulator)
• Various university-hosted remote access systems

For full Quartus functionality, local installation remains necessary.

Which Quartus version should I use for MAX II CPLDs?

For MAX II CPLD development, Quartus 13.1 is the recommended version as it provides full feature support without the overhead of newer releases. Quartus Prime Lite (current versions) also supports MAX II, though some users prefer the lighter footprint of 13.x for simple CPLD projects.

How do I migrate from ModelSim to Questa?

The migration from ModelSim Quartus to Questa-Intel FPGA is largely push-button:

1. Obtain a free Questa license from Intel’s licensing portal
2. Install Questa alongside or instead of ModelSim
3. Most simulation scripts require minimal changes
4. The primary difference is the license requirement for Questa Starter Edition

What happened to Altera Quartus after Intel acquisition?

Intel acquired Altera in December 2015 for $16.7 billion. The software was rebranded from “Altera Quartus” to “Intel Quartus Prime.” In 2024, Intel announced spinning off its FPGA business as a standalone company under the Altera brand, meaning future releases may return to “Altera Quartus” branding while maintaining compatibility with existing Intel Quartus projects.

Advanced Quartus Features for Power Users

Design Space Explorer II

For designs struggling to meet timing or resource goals, the Design Space Explorer II (DSE) tool automates the optimization process. DSE iterates through various compiler settings to find optimal configurations:

1. Open Tools → Design Space Explorer II
2. Select optimization goal (Performance, Area, Power, or Balanced)
3. Configure exploration settings (seed count, parallel compilation)
4. Launch exploration and let DSE run through combinations
5. Review results and apply best settings to your project

From my experience, DSE can recover 10-15% of Fmax improvements on challenging designs, though it requires significant computation time.

Signal Tap Logic Analyzer

The embedded Signal Tap logic analyzer is invaluable for debugging FPGA behavior in real hardware. Unlike traditional oscilloscopes, Signal Tap captures internal signals without requiring external I/O pins:

1. Open Tools → Signal Tap Logic Analyzer
2. Add signals to monitor by browsing the design hierarchy
3. Configure trigger conditions (rising edge, pattern match, etc.)
4. Set sample depth based on available memory resources
5. Compile the design with Signal Tap enabled
6. Connect to hardware and arm the trigger
7. View captured waveforms for analysis

Signal Tap consumes FPGA resources proportional to channel count and sample depth. Plan for approximately 1-5% logic overhead depending on configuration.

Timing Constraints and SDC Files

Professional designs require proper timing constraints. Quartus uses Synopsys Design Constraints (SDC) format:

# Create main clock constraint

create_clock -name clk_50mhz -period 20.000 [get_ports clk]

# Create derived clock

create_generated_clock -name clk_100mhz -source [get_ports clk] \

    -multiply_by 2 [get_pins pll|outclk_0]

# Set false paths for asynchronous signals

set_false_path -from [get_registers reset_sync*]

# Define input/output delays

set_input_delay -clock clk_50mhz -max 5.0 [get_ports data_in*]

set_output_delay -clock clk_50mhz -max 3.0 [get_ports data_out*]

Without proper SDC constraints, the Timing Analyzer cannot accurately report design performance. I’ve seen many designers skip this step and then wonder why their 100MHz design works at room temperature but fails in production.

Incremental Compilation

For large designs, incremental compilation dramatically reduces iteration time by preserving unchanged portions of the design:

1. Create design partitions for stable modules
2. Enable Assignments → Settings → Compilation Process Settings → Incremental Compilation
3. Compile initially to establish baseline
4. Subsequent compilations reuse placement for unmodified partitions

This feature saved me countless hours on a recent Cyclone V project where the core logic was stable but the peripheral interfaces changed frequently during board bring-up.

PCB Design Considerations for Quartus-Based Systems

As someone who works on both FPGA firmware and PCB layout, I want to share some practical hardware considerations that affect your Quartus designs.

Power Supply Requirements

Intel FPGAs typically require multiple voltage rails with specific sequencing:

Rail	Typical Voltage	Notes
VCCINT	1.1V – 1.2V	Core logic (highest current)
VCCIO	1.2V – 3.3V	I/O banks (varies by standard)
VCCPLL	1.1V – 1.2V	PLL analog supply (sensitive)
VCCA	2.5V	Transceiver analog

Use the Power Estimator tool in Quartus early in your design to properly size regulators and thermal solutions. I’ve seen boards fail thermal qualification because someone estimated power based on a partially-utilized design.

Pin Planning Strategy

Before placing components on your PCB, use Quartus Pin Planner to optimize I/O allocation:

1. Group related signals in the same I/O bank
2. Place high-speed interfaces near dedicated pins
3. Reserve dedicated clock inputs for system clocks
4. Consider PCB routing when assigning pin locations
5. Verify I/O standard compatibility within banks

A well-planned pin assignment in Quartus can simplify your PCB layout significantly, reducing layer count and improving signal integrity.

Migrating Between Quartus Versions

Upgrading Projects to Newer Quartus

When upgrading a project to a newer Quartus Prime version:

1. Backup your project completely before any migration
2. Open the project in the new Quartus version
3. Accept prompts to upgrade project files
4. Recompile and check for deprecated features
5. Review IP Core compatibility (may require regeneration)
6. Verify timing results haven’t degraded

Quartus generally maintains backward compatibility, but IP cores often require regeneration when crossing major version boundaries (e.g., 18.1 to 20.1).

Downgrading or Maintaining Legacy Versions

Sometimes you need to maintain older Quartus II versions for legacy projects:

• Install multiple Quartus versions in separate directories
• Use version-specific project files (.qpf, .qsf)
• Consider virtual machines for very old versions (Quartus 9.1, etc.)
• Document version dependencies in your project README

I maintain three Quartus installations on my development machine: 13.1 for Cyclone II legacy projects, 18.1 for stable production work, and the latest for new development.

Scripting and Automation with Tcl

Quartus Tcl Scripting Basics

Quartus supports extensive automation through Tcl scripting. Common uses include:

• Batch compilation across multiple configurations
• Automated pin assignment from spreadsheets
• Custom report generation
• Continuous integration pipeline integration

Example: Batch compilation script

# Load the project

project_open my_project

# Iterate through device variants

foreach device {EP4CE22F17C6 EP4CE22F17C7 EP4CE22F17C8} {

    set_global_assignment -name DEVICE $device

    execute_flow -compile

    # Copy output files with device suffix

    file copy -force output_files/my_project.sof \

        output_files/my_project_${device}.sof

}

project_close

Integration with CI/CD Pipelines

For professional development, integrate Quartus into your build system:

1. Use quartus_sh command-line interface
2. Create scripts for synthesis, fitting, and timing analysis
3. Parse compilation reports for pass/fail criteria
4. Archive programming files as build artifacts

This approach ensures reproducible builds and catches regressions early in the development cycle.

Conclusion

Quartus Prime remains the essential tool for Intel/Altera FPGA development, from simple CPLD projects using MAX II devices to complex SoC designs on Agilex. While the learning curve can be steep, the software provides everything needed for professional FPGA design under one roof.

For those starting out, I recommend beginning with Quartus Prime Lite and a cost-effective development board like the DE10-Lite (MAX 10) or Cyclone IV-based alternatives. As your projects grow more complex, you can evaluate whether the Standard or Pro editions provide enough additional value to justify the Quartus price.

The transition from ModelSim to Questa and the eventual Nios II to Nios V migration represent ongoing evolution in the toolchain. Staying current with releases while maintaining archived versions for legacy projects is simply part of working with programmable logic devices—a balance between innovation and long-term support that every hardware engineer learns to navigate.

Whether you’re downloading Quartus 13.1 for a legacy Cyclone II project, setting up Quartus Prime 20.1 for the last ModelSim-compatible environment, or working with the latest release for cutting-edge Agilex designs, this guide should provide the foundation you need to be productive with Intel’s FPGA development tools.

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