Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.
Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.
Notes: For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.
IPC-7351: Complete Guide to SMD Land Pattern Design & PCB Footprint Standards
Every PCB designer eventually faces the same question: what pad dimensions should I use for this component? Get it wrong, and you’re looking at tombstoning, bridging, insufficient solder joints, or boards that simply won’t assemble properly. After years of creating footprints for everything from 0201 chip resistors to fine-pitch BGAs, I can tell you that IPC-7351 is the standard that answers this question definitively.
IPC-7351 (current revision: IPC-7351B) is the industry standard for surface mount land pattern design. Published by IPC, this comprehensive 102-page document provides the formulas, dimensions, and guidelines needed to create reliable SMD footprints for virtually any component package. Whether you’re designing consumer electronics, automotive systems, or high-reliability aerospace boards, understanding IPC-7351 is essential for creating manufacturable PCBs with reliable solder joints.
What is IPC-7351 and Why Every PCB Designer Needs It
IPC-7351, titled “Generic Requirements for Surface Mount Design and Land Pattern Standard,” replaced the older IPC-SM-782A standard. It provides a systematic approach to calculating pad dimensions that ensure proper solder fillet formation during reflow assembly.
Specification
Details
Document Number
IPC-7351B
Full Title
Generic Requirements for Surface Mount Design and Land Pattern Standard
Current Revision
Revision B (June 2010)
Previous Versions
IPC-7351A (2007), IPC-7351 (2005)
Predecessor Standard
IPC-SM-782A
Page Count
102 pages
Included Tools
Land Pattern Calculator (discontinued 2018)
Publisher
IPC – Association Connecting Electronics Industries
The genius of IPC-7351 is that it doesn’t just give you fixed pad dimensions for each component. Instead, it provides mathematical algorithms that calculate optimal pad sizes based on component dimensions, manufacturing tolerances, and your desired solder fillet goals. This approach accommodates variations between component manufacturers and allows you to tune footprints for your specific assembly process.
Key Features of the IPC-7351 Standard
Feature
Benefit
Three-tier density system
Optimize for high-density, standard, or robust assembly
Standardized naming convention
Universal footprint identification across CAD systems
Zero component orientation
Consistent rotation for pick-and-place automation
Solder fillet goal calculations
Ensures reliable joint formation
Courtyard dimensions
Proper component spacing for assembly and rework
Component family coverage
Guidelines for SOPs, QFPs, BGAs, QFNs, chip components
The Three Density Levels in IPC-7351
One of the most practical features of IPC-7351 is its three-tier density system. Rather than providing a single “one-size-fits-all” footprint for each component, the standard offers three variations based on your design requirements.
General-purpose designs, balanced reliability and density
Least (Minimum)
Level C / M
Smallest pads
High-density boards, mobile devices, space-constrained designs
When to Use Each Density Level
Most (Level A) provides the largest pads and most robust solder joints. Use this when:
Board space is not a constraint
Reliability is critical (medical, aerospace, military)
Manual rework and inspection are expected
You’re prototyping and want margin for error
Nominal (Level B) is the default choice for most designs. Use this when:
Standard component density is acceptable
You need balance between reliability and board size
Working with typical reflow assembly processes
No special density or reliability requirements exist
Least (Level C) creates the smallest compliant footprints. Use this when:
Maximum component density is required
Board size is strictly limited (wearables, IoT, mobile)
Advanced assembly equipment is available
Design for manufacturability has been verified with your CM
Solder Fillet Goals by Density Level
The density levels directly affect the solder fillet dimensions (J-values) used in pad calculations:
Fillet Type
Most (Level A)
Nominal (Level B)
Least (Level C)
Toe Fillet (Jt)
0.55 mm
0.35 mm
0.15 mm
Heel Fillet (Jh)
0.45 mm
0.35 mm
0.25 mm
Side Fillet (Js)
0.05 mm
0.03 mm
0.01 mm
These J-values represent the target solder fillet extensions beyond the component lead. Larger values create more robust joints but consume more board space.
IPC-7351 Land Pattern Calculation Formulas
Understanding how IPC-7351 calculates pad dimensions helps you verify footprints and troubleshoot assembly issues. The standard uses a tolerance-based approach that accounts for component dimensional variations.
Primary Land Pattern Dimensions
For a typical two-terminal chip component or leaded package, IPC-7351 calculates three key dimensions:
Dimension
Symbol
Description
Pad Span (outer)
Z
Distance across the outer edges of both pads
Pad Gap (inner)
G
Distance between the inner edges of both pads
Pad Width
Y
Width of each pad (perpendicular to component)
Pad Length
X
Calculated from Z and G: X = (Z – G) / 2
Pad Center
C
Center-to-center distance: C = (Z + G) / 2
The Calculation Algorithm
The IPC-7351 calculation considers component tolerances and manufacturing variations:
Parameter
Description
L
Component length (overall body or lead span)
T
Terminal/lead length (measured from body edge)
W
Terminal/lead width
S
Distance between terminals (internal span)
F
Fabrication tolerance (typically 0.05 mm)
P
Placement tolerance (typically 0.025 mm for modern equipment)
The formulas incorporate Root Mean Square (RMS) tolerance analysis:
For outer dimension Z: Z = Lmax + 2(Jt) + √(Ltol² + 4F² + 4P²)
For inner dimension G: G = Smin – 2(Jh) – √(Stol² + 4F² + 4P²)
For pad width Y: Y = Wmax + 2(Js) + √(Wtol² + 4F² + 4P²)
Where tolerances are calculated as: Ltol = Lmax – Lmin, etc.
Practical Example: 0805 Chip Resistor
Let’s walk through a real calculation for a common 0805 chip resistor:
Component Dimension
Min (mm)
Max (mm)
Tolerance
Length (L)
1.80
2.20
0.40
Terminal Length (T)
0.30
0.60
0.30
Width (W)
1.10
1.40
0.30
Using Nominal density (Level B) with Jt = 0.35, Jh = 0.35, Js = 0.03:
Calculated Dimension
Value (mm)
Z (outer span)
2.95
G (gap)
0.75
X (pad length)
1.10
Y (pad width)
1.45
C (center-to-center)
1.85
IPC-7351 Naming Convention for Component Footprints
The IPC-7351 naming convention creates a standardized way to identify footprints that works across all CAD systems. This “One World CAD Library” approach ensures that when you specify a footprint name, anyone can understand exactly what it represents.
Naming Convention Structure
Element
Description
Example
Component Family
Package type identifier
CAPC, RESC, SOIC, QFP, BGA
Body Length
Length in mm × 100
2012 = 2.0 × 1.2 mm
Body Width
Width in mm × 100
(included in length)
Height
Height in mm × 100
X80 = 0.80 mm
Pin Count
Number of terminals
-8 = 8 pins
Density
L, N, or M suffix
N = Nominal
Common Footprint Name Examples
IPC-7351 Name
Component Description
CAPC1608X90N
0603 capacitor, 0.9mm height, Nominal density
RESC2012X65L
0805 resistor, 0.65mm height, Least density
SOIC127P600X175-8N
SOIC-8, 1.27mm pitch, 6mm body, Nominal
QFP50P1200X1200X160-64N
QFP-64, 0.5mm pitch, 12×12mm body
BGA127P13X13_1524X1524X185-169N
169-ball BGA, 1.27mm pitch
Family Codes for Common Components
Family Code
Component Type
CAPC
Chip Capacitor (non-polarized)
CAPMP
Chip Capacitor (polarized/tantalum)
RESC
Chip Resistor
INDC
Chip Inductor
DIOM
Molded Diode
SOTFL
Small Outline Transistor, Flat Lead
SOIC
Small Outline Integrated Circuit
SOP
Small Outline Package
QFP
Quad Flat Package
QFN
Quad Flat No-Lead
SON
Small Outline No-Lead
BGA
Ball Grid Array
Component Family Coverage in IPC-7351
IPC-7351 provides specific guidelines for major component families. The standard is supplemented by the IPC-735x series for detailed requirements:
Leadless packages like QFN and SON require special attention in IPC-7351:
Consideration
Guideline
Thermal Pad
Typically 80-90% of exposed pad size
Thermal Via Pattern
Array of vias connected to ground plane
Pad Extension
Minimal toe extension (leads are under package)
Solder Paste
Reduced aperture on thermal pad (25-50% coverage)
Soldermask
Gang mask or individual windows per process
BGA Package Guidelines
BGA Parameter
IPC-7351 Recommendation
Pad Shape
Non-solder mask defined (NSMD) preferred
Pad Diameter
Ball diameter minus 0.1mm typical
Soldermask Opening
Pad diameter plus 0.1mm
Via-in-Pad
Filled and planarized if used
Pitch Categories
1.27mm, 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm
Courtyard Dimensions and Component Spacing
IPC-7351 defines courtyard boundaries that establish minimum clearances around components. The courtyard includes the component body, leads, and required clearance for assembly and rework equipment.
Courtyard Excess by Density Level
Density Level
Courtyard Excess
Application
Most (Level A)
0.50 mm
Adequate clearance for rework tools
Nominal (Level B)
0.25 mm
Standard clearance for most assembly
Least (Level C)
0.10 mm
Minimum viable clearance
Component Spacing Guidelines
Spacing Consideration
Recommendation
Minimum pad-to-pad
Based on soldermask dam capability
Component-to-component
Courtyard boundaries should not overlap
Component-to-edge
Minimum 2.5mm from board edge (panelization)
Tall components
Additional clearance for reflow shadowing
IPC-7351 Zero Component Orientation
The standard defines a Zero Component Orientation to ensure all CAD libraries use consistent rotation. This seemingly minor detail has major implications for assembly automation.
Component Type
Zero Orientation
Two-terminal chip
Pin 1 (positive/cathode) on left
Polarized capacitors
Positive terminal on left
Diodes
Cathode on left
SOICs/QFPs
Pin 1 at upper left corner
BGAs
A1 ball at upper left
This standardization allows pick-and-place files to use consistent rotation values across different component libraries and CAD systems.
IPC-7351 vs IPC-SM-782: What Changed
IPC-7351 replaced the older IPC-SM-782A standard with significant improvements:
Aspect
IPC-SM-782A
IPC-7351
Approach
Fixed dimensions per package
Calculated from tolerances
Density Options
Single footprint per package
Three density levels (M/N/L)
Naming Convention
Informal
Standardized, machine-readable
Component Rotation
Varied by library
Zero orientation standard
Calculator Tools
None
Land Pattern Calculator included
Tolerance Handling
Approximate
RMS statistical analysis
Modern Packages
Limited coverage
QFN, SON, fine-pitch BGA
Land Pattern Calculators and Design Tools
While IPC discontinued the original calculator in 2018, several tools remain available for IPC-7351 calculations:
What is the difference between IPC-7351 and IPC-7351B?
IPC-7351B is the current revision, released in June 2010, updating the original IPC-7351 (2005) and IPC-7351A (2007). Revision B added coverage for additional component families including resistor array packages, aluminum electrolytic capacitors, column and land grid arrays, flat lead devices (SODFL and SOTFL), and dual flat no-lead (DFN) devices. It also introduced thermal tab guidance and a new padstack naming convention for multi-layer land patterns.
How do I choose between Most, Nominal, and Least density in IPC-7351?
Start with Nominal (Level B) as your default for general-purpose designs. Choose Most (Level A) when reliability is critical, manual rework is expected, or board space is not constrained. Choose Least (Level C) only when maximum component density is required and your contract manufacturer has confirmed their assembly process can handle tighter tolerances. Always consult with your CM before finalizing density level selection.
Where can I find an IPC-7351 land pattern calculator?
The original IPC-7351 calculator was discontinued in 2018. Current alternatives include PCB Libraries Footprint Expert (commercial), Altium Designer’s built-in IPC Compliant Footprint Wizard, KiCad’s footprint calculator, and free online resources from Ultra Librarian, SnapEDA, and SamacSys. Most modern PCB CAD tools include some form of IPC-7351 compliant footprint generation capability.
What are the J-values (Jt, Jh, Js) in IPC-7351 calculations?
J-values represent the solder fillet goals for toe (Jt), heel (Jh), and side (Js) fillets. These values define how much solder should extend beyond the component lead in each direction. Larger J-values create more robust solder joints but require larger pads. The three density levels (Most, Nominal, Least) use different J-values, with Most having the largest fillets and Least having the smallest.
Does IPC-7351 apply to through-hole components?
IPC-7351 primarily covers surface mount technology (SMT) components. However, it does reference IPC-7357 for through-hole (DIP) leads with posts on two sides. For comprehensive through-hole design guidance, refer to IPC-2221 (PCB design) and IPC-7251 (through-hole land pattern requirements). The IPC-735x family collectively addresses both surface mount and through-hole technologies.
Conclusion
IPC-7351 provides the foundation for creating reliable SMD footprints that work consistently across different assembly houses and component manufacturers. By understanding the three density levels, the calculation algorithms, and the standardized naming conventions, you can create PCB designs that assemble correctly the first time.
The key takeaways are straightforward: always select an appropriate density level for your application, verify your footprints against IPC-7351 calculations rather than blindly trusting manufacturer recommendations, pay special attention to leadless packages like QFN and BGA, and maintain consistent zero orientation across your CAD library. These practices will reduce assembly defects, improve first-pass yield, and ultimately save time and money in your product development cycle.
Whether you’re creating footprints from scratch or validating existing libraries, IPC-7351 gives you the technical foundation to make informed decisions about pad dimensions and component spacing. Invest the time to understand these principles, and your boards will reflect that attention to detail in their assembly quality and long-term reliability.
Inquire: Call 0086-755-23203480, or reach out via the form below/your sales contact to discuss our design, manufacturing, and assembly capabilities.
Quote: Email your PCB files to Sales@pcbsync.com (Preferred for large files) or submit online. We will contact you promptly. Please ensure your email is correct.
Notes: For PCB fabrication, we require PCB design file in Gerber RS-274X format (most preferred), *.PCB/DDB (Protel, inform your program version) format or *.BRD (Eagle) format. For PCB assembly, we require PCB design file in above mentioned format, drilling file and BOM. Click to download BOM template To avoid file missing, please include all files into one folder and compress it into .zip or .rar format.
