Radiation-Hardened Options:

• LEON3FT / LEON5:
  SPARC V8 architecture, SEU immune, 100+ krad TID, widely used in ESA missions. Clock: up to 250 MHz, ideal for GEO/MEO missions.
• BAE RAD750:
  PowerPC architecture, 1000+ krad TID, >10^15 SEU immunity. Used in Mars rovers, James Webb Telescope. Clock: 200 MHz, highest reliability.
• ARM Cortex-R5 (RT variant):
  Modern architecture with lockstep cores, 50-100 krad TID. Clock: up to 600 MHz, good for LEO/MEO missions with EDAC.
• Microchip RTG4 FPGA:
  Flash-based FPGA immune to configuration upset, 50 krad TID, no SEU in configuration. Flexible, reprogrammable solution.

Commercial Off-The-Shelf (COTS):

• TI MSP430FR:
  Ultra-low power, FRAM memory, good for LEO CubeSats. 16-bit, up to 24 MHz. TID: ~20 krad with proper shielding.
• STM32L4+ Series:
  ARM Cortex-M4, low power, extensive peripherals. Clock: up to 120 MHz. Suitable for LEO with software mitigation (TMR, watchdogs).
• Microchip SAMA5D2:
  ARM Cortex-A5, 500 MHz, Linux capable. Good for LEO missions requiring complex processing with adequate shielding.

DC-DC Converters:

• Vicor DCM Series:
  High efficiency (>94%), 50-300W, wide input range (12-48V), isolated outputs. Excellent for satellite bus power distribution.
• TI TPS63900 (Buck-Boost):
  2A output, 93% efficiency, ultra-low IQ (75nA). Ideal for battery-powered subsystems. Wide VIN: 1.8V-5.5V.
• Analog Devices ADP1613:
  Step-up DC-DC, 1.2A, 90% efficient. Good for solar MPPT applications in CubeSats.

LDO Regulators:

• TI TPS7A47 (Radiation Tolerant):
  Ultra-low noise (4.17µVrms), 1A output, excellent PSRR. 30 krad TID tested. Perfect for sensitive RF/analog circuits.
• Analog Devices ADP7182:
  200mA, ultra-low IQ (18µA), wide temp range (-55°C to +125°C). Good for low-power sensor nodes.

Battery Management:

• BQ76952 (TI):
  3-16 cell Li-ion BMS, integrated cell balancing, accurate voltage sensing (±5mV). Autonomous protection features.
• LTC4015 (Analog Devices):
  Multi-chemistry buck-boost charger, MPPT for solar, I²C telemetry. Up to 3.2A charge current. Excellent for CubeSat power systems.

Transceivers:

• Analog Devices AD9361 / AD9364:
  RF Agile Transceiver, 70 MHz – 6 GHz, 2×2 MIMO, integrated synthesizer. Software-defined radio capability. Power: 1.3W typical.
• TI CC1352R (Sub-GHz):
  Multi-band wireless MCU: 2.4 GHz + Sub-1 GHz (433/868/915 MHz). +20dBm output, -124dBm sensitivity. Ideal for IoT satellite links.
• Semtech SX1262 (LoRa):
  Long-range, low-power, 150-960 MHz. -148dBm sensitivity, +22dBm output. Good for CubeSat downlinks with ground stations.

Power Amplifiers:

• Qorvo TGA2595 (S-band):
  2-2.5 GHz, +43dBm P1dB, 50% PAE. Space heritage, high linearity. Typical use: 2.2 GHz downlink transmitters.
• Wolfspeed CGHV1J025D (Ka-band):
  GaN HEMT, 25W, 26-40 GHz. Excellent for high-throughput Ka-band communications. Requires careful thermal design.

Frequency Synthesis:

• Analog Devices ADF4371:
  Wideband synthesizer, 62.5 MHz – 32 GHz, ultra-low phase noise (-232 dBc/Hz @ 10 kHz offset). Integrated VCO.

SRAM (Radiation Hardened):

• Renesas (Intersil) ISS16LV16256:
  4Mb SRAM, 300 krad TID, SEU immune, -55°C to +125°C. Space-qualified, QML Class V available.
• Cypress (Infineon) CY62167GE30:
  16Mb SRAM, 100 krad TID, industrial temp. Good for LEO missions with EDAC.

Flash & EEPROM:

• Microchip SST39VF series:
  NOR Flash, up to 32Mb, 50 krad TID. Byte-programmable, suitable for boot code and configuration.
• STMicroelectronics M95M04:
  4Mb SPI EEPROM, 30 krad TID, 1M write cycles. Good for telemetry data logging.

FRAM (Best for Space):

• Fujitsu MB85RS4MT:
  4Mb FRAM, SPI interface, 10^13 write cycles, no write delay. Inherently radiation tolerant (up to 100 krad). Perfect for frequent data logging.

Attitude Determination:

• Analog Devices ADIS16485 (IMU):
  10-DOF, ±450°/s gyro, ±18g accel, magnetometer. SPI output, low noise. Industrial temp range, suitable for LEO with mitigation.
• STMicroelectronics LSM6DSO (6-axis):
  Ultra-low power IMU, I²C/SPI, machine learning core. Good for CubeSat ADCS with redundancy.

Temperature & Current Sensing:

• TI TMP117:
  High-accuracy digital temp sensor (±0.1°C), I²C, -55°C to +150°C range. Low power (3.5µA active).
• TI INA226:
  Precision current/power monitor, 16-bit ADC, I²C. ±81.92mV shunt voltage. Essential for power budget monitoring.

ADC/DAC:

• Analog Devices AD7980 (ADC):
  16-bit SAR ADC, 1 MSPS, ultra-low power (8mW). SPI output, excellent for telemetry acquisition.
• TI DAC80501 (DAC):
  16-bit DAC, SPI/I²C, internal reference, low glitch. Good for actuator control and calibration.

Mission Requirements:

• Orbit Type: LEO, MEO, or GEO determines radiation levels, thermal environment, and mission duration
• Mission Duration: Defines component lifetime requirements and redundancy needs
• Environmental Conditions: Temperature range, radiation dose (TID, SEE), vacuum, vibration levels
• Power Budget: Available power from solar panels and batteries, eclipse duration
• Mass Budget: Allocated mass for PCB subsystem (typically 5-15% of total satellite mass)
• Size Constraints: CubeSat standard (10×10cm), custom form factor, stacking requirements

Functional Requirements:

• Subsystem Definition: Command & Data Handling (C&DH), Power, Communications, Attitude Control, Payload
• Interface Requirements: Connector types, signal levels, protocols (I²C, SPI, CAN, SpaceWire)
• Performance Specs: Data rates, processing power, frequency bands, power consumption
• Reliability Requirements: MTBF targets, redundancy level, graceful degradation strategy

Standards & Compliance:

• ECSS (European Cooperation for Space Standardization): ECSS-Q-ST-70-60C for derating
• NASA standards: NASA-STD-8739.3 (soldering), NASA-STD-8739.4 (crimping)
• IPC standards: IPC-6012 Class 3, IPC-A-610 Class 3 (space applications)
• MIL-STD-883 for component qualification
• Radio frequency allocations: ITU Radio Regulations for frequency coordination

System Architecture:

• Block Diagram Creation: Define all subsystems, interfaces, and data flows
• Power Architecture: Solar panel regulation, battery charging, power distribution, bus voltage selection (typically 3.3V, 5V, 12V, 28V)
• Processing Architecture: Main processor selection, co-processors, FPGA vs ASIC trade-offs
• Communication Architecture: RF chain design, modulation schemes, antenna interfaces
• Redundancy Strategy: Hot vs cold redundancy, cross-strapping, autonomous switching

Component Selection Process:

• Radiation Hardness: Match IC TID rating to mission requirements (LEO: 10-50 krad, MEO: 50-200 krad, GEO: 100-500 krad)
• Temperature Range: Verify operation from -55°C to +125°C (or mission-specific range)
• Space Heritage: Prioritize components with flight history, check NASA NEPP program
• Derating Guidelines: Voltage: 50% derating, Current: 70% derating, Power: 60% derating, Temperature: 80% of max junction temp
• Obsolescence Risk: Choose components with long lifecycle, identify second sources
• Procurement Strategy: QML (Qualified Manufacturers List) Class V for critical parts, screening requirements

Key Design Trade-offs:

• Rad-Hard vs COTS: Rad-hard: higher reliability, proven, expensive, limited selection. COTS: cheaper, more features, requires mitigation (TMR, EDAC)
• Power vs Performance: Higher clock speeds = more processing but higher power consumption and thermal load
• Analog vs Digital: Analog: less power, simpler, harder to mitigate SEU. Digital: more flexible, easier error correction
• Board Complexity: More layers = better signal integrity but higher cost and longer lead time

Schematic Best Practices:

• Hierarchical Design: Use hierarchical blocks for each subsystem, create reusable sub-circuits
• Power Sequencing: Design proper power-up and power-down sequences, add enable pins and power-good signals
• Reset Strategy: Implement power-on reset (POR), watchdog timer, manual reset button with debouncing
• Decoupling: 0.1µF ceramic + 10µF tantalum at every IC, place close to power pins (<5mm)
• ESD Protection: TVS diodes on all external interfaces, series resistors (100-1kΩ) on sensitive inputs
• EMI Filtering: Common-mode chokes on power inputs, ferrite beads on noisy supplies, LC filters where needed

Critical Circuit Sections:

• Power Supply Design: MPPT for solar input, battery charge controller with cell balancing, multiple DC-DC converters for different voltages, overcurrent and overvoltage protection, current sensing for telemetry
• Clock Distribution: Use crystal oscillators with proper loading capacitors, implement clock buffers for fanout, add termination resistors for high-speed clocks
• Memory Interface: Implement EDAC for SRAM/DRAM, add checksum verification for Flash, use scrubbing for configuration memory
• Communication Interfaces: Differential pairs for high-speed (USB, Ethernet), proper termination (100Ω for USB, 120Ω for CAN), isolation transformers where needed

Design Reviews:

• Internal Review: Check power budget, verify all connections, validate component ratings
• Preliminary Design Review (PDR): Present to stakeholders, verify requirements compliance, identify risks
• Peer Review: Have experienced engineers review for common pitfalls
• Design Rule Check (DRC): Use EDA tool electrical rules checking, verify pin assignments

Layout Preparation:

• Board Outline: Define mechanical dimensions, mounting hole locations, keepout zones
• Layer Stackup: Select appropriate number of layers (typically 4-10 for satellites)
• Design Rules: Set minimum trace width (6mil), spacing (6mil), via size (0.3mm), annular ring (0.15mm)
• Component Library: Create accurate footprints, verify against datasheets, include 3D models for mechanical clearance

Component Placement Strategy:

• Power Section: Place power supplies and converters first, minimize input-to-output trace lengths, keep switching nodes short (<20mm)
• Processor & Memory: Keep close together (within 50mm), place decoupling caps immediately adjacent, provide solid ground plane underneath
• RF Section: Isolate RF components, use ground guard rings, maintain 50Ω impedance to antenna connector
• Analog Section: Separate from digital noise sources, use dedicated ground area, place away from power switching circuits
• Connectors: Place on board edges, align with mechanical interface, provide strain relief consideration

Routing Guidelines:

• Power Routing: Use 20-40mil traces for main power distribution, calculate trace width for current capacity (1A per 10mil for 1oz copper), use polygon pours for high-current paths
• High-Speed Signals: Route as differential pairs with 5mil spacing, match lengths within 1mm, minimize layer changes, add via shielding for EMI
• Impedance Control: Maintain 50Ω single-ended or 100Ω differential for RF and high-speed digital, use impedance calculator for trace width
• Ground Planes: Provide continuous ground plane, avoid splits in plane (except intentional analog/digital separation), use ground stitching vias every 10mm
• Via Design: Use 0.3-0.5mm diameter, maintain adequate annular ring, add thermal relief for hand soldering, avoid vias in pads for BGA

Thermal Management:

• Thermal Vias: Array of 0.3mm vias under power components (0.7mm pitch), directly connect to thermal pads on bottom layer
• Copper Pour: Use solid copper pour on inner layers for heat spreading, connect to component thermal pads
• Component Spacing: Maintain 10mm clearance around high-power components, prevent thermal hotspots
• Thermal Interface: Design mounting holes for heat spreaders or cold plates, add thermal compound application areas

Manufacturing Considerations:

• Fiducials: Add 3 global fiducials (1mm diameter) for panel alignment, local fiducials for fine-pitch ICs
• Silkscreen: Add reference designators, polarity marks, test point labels, “No Clean” zone marks, company logo
• Soldermask: Use space-qualified soldermask (green or black), define soldermask openings for test points
• Surface Finish: ENIG (Electroless Nickel Immersion Gold) preferred for space applications, 50µin Au over 120-240µin Ni

Signal Integrity Analysis:

• Impedance Analysis: Verify controlled impedance traces meet target ±10%, check with 2D field solver
• Crosstalk Analysis: Ensure <10% far-end crosstalk on critical signals, add guard traces if needed
• Eye Diagram: Simulate high-speed interfaces (USB, Ethernet), verify eye opening meets specifications
• Return Loss: Check S11 < -10dB for RF traces, optimize matching networks

Power Integrity Analysis:

• DC Drop: Calculate voltage drop on power traces, verify <100mV drop from source to load
• AC Impedance: Check power plane impedance <1Ω up to 100MHz, add additional decoupling if needed
• Transient Response: Simulate load step response, verify <5% overshoot/undershoot

Thermal Analysis:

• FEA Simulation: Model worst-case thermal scenario (eclipse + full load), verify junction temps <100°C
• Hotspot Identification: Locate thermal bottlenecks, add thermal vias or heat spreaders as needed
• Thermal Cycling: Verify design survives -55°C to +125°C cycling without CTE mismatch failures

EMI/EMC Analysis:

• Radiated Emissions: Predict EMI from switching converters, high-speed clocks, and RF sections
• Conducted Emissions: Verify filtering on power lines meets requirements
• Susceptibility: Ensure design can withstand external EMI per MIL-STD-461

DRC & Verification:

• Design Rule Check: Run full DRC in EDA tool, resolve all errors and critical warnings
• Netlist Comparison: LVS (Layout vs Schematic) check, verify 100% match
• Manufacturability: DFM check for fabrication issues, review with PCB vendor
• Assembly Review: Check component accessibility, verify clearance for assembly tooling

PCB Fabrication:

• Vendor Selection: Choose space-qualified PCB manufacturer (AS9100 certified), verify capability for RF materials
• Stackup Specification: Provide detailed stackup with material callouts, impedance requirements, copper weights
• Quality Requirements: Specify IPC-6012 Class 3, require impedance testing (100% for RF layers), request first article inspection
• Lead Time: Typical 4-6 weeks for standard boards, 8-12 weeks for complex RF/high-layer-count

PCB Assembly (PCBA):

• Stencil Design: Create custom stencil with optimized apertures, use step stencil for mixed component heights
• Solder Paste: Use space-qualified solder paste (SAC305 or similar), proper storage and handling
• Pick-and-Place: Program with accurate component library, verify orientation and polarity
• Reflow Profile: Optimize temperature profile for lead-free solder, typical peak 245-250°C for 30-60 seconds
• Inspection: AOI (Automated Optical Inspection) after reflow, X-ray for BGA packages, manual inspection for critical areas
• Hand Soldering: Use controlled soldering station (NASA-STD-8739.3), verify workmanship to IPC-A-610 Class 3

Conformal Coating:

• Preparation: Clean board (IPA ultrasonic), bake at 80°C to remove moisture, mask connectors and test points
• Application: Apply Parylene C (preferred) or acrylic coating (25-50µm thickness), use spray or dip method
• Curing: Follow manufacturer cure schedule, typically room temp for 24hrs or 60°C for 4hrs
• Inspection: Verify uniform coverage, check for voids or runs, measure thickness

Documentation:

• As-Built Documentation: Record any deviations from design, photograph completed boards, maintain traceability
• Material Certification: Collect material certs for all components, PCB laminate, solder, and coatings
• Serial Numbers: Assign unique identifiers to each board, maintain inventory database

Functional Testing:

• Power-On Test: Verify power sequencing, measure voltage rails (±2% tolerance), check current consumption
• Interface Testing: Test all communication interfaces (UART, I²C, SPI, CAN), verify data integrity
• Performance Verification: Measure clock frequencies, check ADC/DAC linearity, verify timing
• End-to-End Testing: Run complete functional test suite, verify against requirements specification

Environmental Testing:

• Thermal Cycling: -55°C to +85°C (or mission-specific range), 10-20 cycles minimum, functional test at temperature extremes
• Thermal Vacuum (TVAC): Operate in vacuum chamber (<10^-5 torr), thermal cycling in vacuum, verify outgassing <1% TML, duration: 72hrs minimum
• Vibration Testing: Random vibration per NASA-STD-7001 (14.1 Grms overall), swept sine (5-2000 Hz), duration: 2 minutes per axis (3 axes), functional test after each axis
• Shock Testing: 30-100g depending on mission, half-sine pulse, functional test immediately after

Radiation Testing:

• Total Ionizing Dose (TID): Expose to Co-60 gamma source, test at 10%, 30%, 50%, 70%, 100%, and 200% of mission dose, functional test at each level, typical rate: 50-300 rad/s
• Single Event Effects (SEE): Heavy ion testing at cyclotron facility, map SEU cross-section vs LET, verify no SEL (latchup) up to LETTH, test representative component samples
• Proton Testing: For MEO/GEO missions, expose to proton beam (50-200 MeV), measure displacement damage effects

EMI/EMC Testing:

• Radiated Emissions: Test in anechoic chamber per MIL-STD-461, verify compliance from 30 MHz to 40 GHz
• Conducted Emissions: Measure on power lines, verify filtering effectiveness
• Radiated Susceptibility: Expose to external fields up to 200 V/m, verify continued operation
• ESD Testing: Apply ±8kV contact discharge, ±15kV air discharge per IEC 61000-4-2, verify no damage or upset

Life Testing:

• Burn-In: Operate at elevated temperature (85°C) for 168-1000 hours, identify early failures, measure drift in critical parameters
• Thermal Cycling: Extended cycling (100-500 cycles) to verify solder joint reliability, measure resistance increase in critical paths
• Power Cycling: 1000-10000 cycles of power on/off, verify no degradation in startup behavior

Flight Acceptance Testing:

• Workmanship Inspection: 100% visual inspection per IPC-A-610 Class 3, X-ray of all BGA packages, cross-section analysis of representative solder joints
• Final Functional Test: Complete functional test suite at room temperature, verify all requirements, generate test report
• Integration Testing: Test with other satellite subsystems, verify interfaces, conduct end-to-end system test